University of Illinois Urbana-Champaign

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Showing 61–90 of 647 items
Thumbnail for Parallel Processing for VLSI Simulation
Parallel Processing for VLSI Simulation
Mueller-Thuns, Robert Bernard

Thumbnail for Fast and Accurate CMOS Bridging Fault Simulation
Fast and Accurate CMOS Bridging Fault Simulation
Rearick, Jeffrey R.

Thumbnail for Illinois Technograph v. 099, iss. 5 Apr. 1984
Illinois Technograph v. 099, iss. 5 Apr. 1984
Submitter: Sarah Shreeves

Thumbnail for Techniques for automatic test knowledge extraction from compiled circuits
Techniques for automatic test knowledge extraction from compiled circuits
Thearling, Kurt Henry

Thumbnail for Parallel-Concurrent Versus Concurrent Fault Simulation
Parallel-Concurrent Versus Concurrent Fault Simulation
Saab, Daniel Georges; Rahmeh, Joseph T.; Hajj, Ibrahim N.

Thumbnail for Functional models for MOS VLSI circuits
Functional models for MOS VLSI circuits
Wehbeh, Jalal Anis

Thumbnail for Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
Prabhakaran, Pradeep; Banerjee, Prithviraj

Thumbnail for Compressed and dynamic fault dictionaries for fault isolation
Compressed and dynamic fault dictionaries for fault isolation
Ryan, Paul George

Thumbnail for A Parallel Simulated Annealing Algorithm for Standard Cell Placement on a Hypercube Computer
A Parallel Simulated Annealing Algorithm for Standard Cell Placement on a Hypercube Computer
Jones, Mark Howard

Thumbnail for Parallel Algorithms for State Assignment of Finite State Machines
Parallel Algorithms for State Assignment of Finite State Machines
Hasteer, Gagan

Thumbnail for Built-In Tests for VLSI Finite-State Machines
Built-In Tests for VLSI Finite-State Machines
Hua, Kien Anh

Thumbnail for Fault-Sensitivity and Wear-Out Analysis of VLSI Systems
Fault-Sensitivity and Wear-Out Analysis of VLSI Systems
Choi, Gwan Seung

Thumbnail for Techniques for Reducing Diagnostic Simulation Time for Partial Scan Circuits
Techniques for Reducing Diagnostic Simulation Time for Partial Scan Circuits
Drummonds, Scott Brady

Thumbnail for Routing algorithms in the physical design of VLSI circuits
Routing algorithms in the physical design of VLSI circuits
Cong, Jingsheng

Thumbnail for The Mesh of Trees Architecture for Parallel Computation
The Mesh of Trees Architecture for Parallel Computation
Hornick, Scot Wayne

Thumbnail for Analysis of Clock Skew in Distributed Resistive-Capacitive Interconnects
Analysis of Clock Skew in Distributed Resistive-Capacitive Interconnects
Gura, Carol Valentina

Thumbnail for Time-based strategies for semiconductor manufacture and test
Time-based strategies for semiconductor manufacture and test
Levitt, Marc Elliot

Thumbnail for A Parallel Algorithm for Switch-Level Timing Simulation on a Hypercube Multiprocessor
A Parallel Algorithm for Switch-Level Timing Simulation on a Hypercube Multiprocessor
Rao, Hariprasad Nannapaneni

Thumbnail for Parallel processing for VLSI simulation
Parallel processing for VLSI simulation
Mueller-Thuns, Robert Bernard

Thumbnail for A Parallel VLSI Architecture for Sparse Matrix Computation
A Parallel VLSI Architecture for Sparse Matrix Computation
Hsu, Peter Yan-Tek

Thumbnail for Reliability Driven Synthesis of Sequential Circuits
Reliability Driven Synthesis of Sequential Circuits
Hsu, Frank F.; Hsiao, Michael S.; Banerjee, Prithviraj

Thumbnail for An Accurate Timing Model for Fault Simulation in MOS Circuits
An Accurate Timing Model for Fault Simulation in MOS Circuits
Kim, Sungho

Thumbnail for Computer technology: A forecast for the future
Computer technology: A forecast for the future
Kubitz, William J.

Thumbnail for Parallel algorithms for standard cell placement using simulated annealing
Parallel algorithms for standard cell placement using simulated annealing
Chandy, John A.

Thumbnail for The Complexity of Test Generation at the Transistor Level
The Complexity of Test Generation at the Transistor Level
Najm, Farid; Hajj, Ibrahim

Thumbnail for MISP, a Multiple Instruction Stream Shared Pipeline Microprocessor
MISP, a Multiple Instruction Stream Shared Pipeline Microprocessor
Archer, David William

Thumbnail for Parallel Architecture for Concurrent Fault Simulation
Parallel Architecture for Concurrent Fault Simulation
Stein, Andrew James

Thumbnail for Determining application-specific peak power and energy requirements for ultra-low-power processors
Determining application-specific peak power and energy requirements for ultra-low-power processors
Ye, Weidong

Thumbnail for Report on Workshop on High Performance Computing and Communications for Grand Challenge Applications: Computer Vision, Speech and Natural Language Processing, and Artificial Intelligence
Report on Workshop on High Performance Computing and Communications for Grand Challenge Applications: Computer Vision, Speech and Natural Language Processing, and Artificial Intelligence
Wah, Benjamin W.

Thumbnail for A class library approach to concurrent object-oriented programming with applications to VLSI CAD
A class library approach to concurrent object-oriented programming with applications to VLSI CAD
Parkes, Steven Michael