University of Illinois Urbana-Champaign

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Showing 1–30 of 647 items
Thumbnail for The Use of Parallel Processing in VLSI Computer-Aided Design Applications
The Use of Parallel Processing in VLSI Computer-Aided Design Applications
Banerjee, Prith

Thumbnail for A New Methodology for VLSI Layout
A New Methodology for VLSI Layout
Sarrafzadeh, M.; Preparata, F.P.

Thumbnail for On Problem Transformability in VLSI
On Problem Transformability in VLSI
Hornick, Scot; Sarrafzadeh, Majid

Thumbnail for ProperCAD II: A Run-Time Library for Portable, Parallel, Object-Oriented Programming with Applications to VLSI CAD
ProperCAD II: A Run-Time Library for Portable, Parallel, Object-Oriented Programming with Applications to VLSI CAD
Parkes, Steven; Chandy, John A.; Banerjee, Prithviraj

Thumbnail for ProperCAD: A Portable Object-Oriented Parallel Environment for VLSI CAD
ProperCAD: A Portable Object-Oriented Parallel Environment for VLSI CAD
Ramkumar, Balkrishna; Banerjee, Prithviraj

Thumbnail for Algorithms for VLSI Routing
Algorithms for VLSI Routing
Zhou, Dian

Thumbnail for A Class Library Approach to Concurrent Object-Oriented Programming with Applications to VLSI CAD
A Class Library Approach to Concurrent Object-Oriented Programming with Applications to VLSI CAD
Parkes, Steven Michael

Thumbnail for Parallel Processing for VLSI CAD Applications a Tutorial
Parallel Processing for VLSI CAD Applications a Tutorial
Banerjee, Prith

Thumbnail for Maximum Switching Activity Estimation for CMOS VLSI Circuits
Maximum Switching Activity Estimation for CMOS VLSI Circuits
Bobba, Sudhakar

Thumbnail for New Techniques for Probabilistic Simulation of VLSI CMOS Circuits
New Techniques for Probabilistic Simulation of VLSI CMOS Circuits
Stamoulis, Georgios I.

Thumbnail for Compressed and Dynamic Fault Dictionaries for Fault Isolation
Compressed and Dynamic Fault Dictionaries for Fault Isolation
Ryan, Paul George

Thumbnail for Switch-Level Test Generation for MOS VLSI Circuits
Switch-Level Test Generation for MOS VLSI Circuits
Najm, Farid Nasri

Thumbnail for Rule-Based Circuit Optimization for CMOS VLSI
Rule-Based Circuit Optimization for CMOS VLSI
Lai, Feipei

Thumbnail for An Optimum Channel Routing Algorithm in the Restricted Wire Overlap Model
An Optimum Channel Routing Algorithm in the Restricted Wire Overlap Model
Zhou, Dian

Thumbnail for A Provably Good Linear Algorithm for Embedding Graphs in the Rectilinear Grid
A Provably Good Linear Algorithm for Embedding Graphs in the Rectilinear Grid
Tamassia, Roberto; Tollis, Ioannis G.

Thumbnail for Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
Reconfigurable Tree Architectures Using Subtree Oriented Fault Tolerance
Lowrie, Matthew B.

Thumbnail for A Heuristic for Manhattan Routing
A Heuristic for Manhattan Routing
Lodi, E.; Preparata, F.P.

Thumbnail for Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Saab, Daniel Georges

Thumbnail for Design and Synthesis for Testability Using Architectural Descriptions
Design and Synthesis for Testability Using Architectural Descriptions
Chickermane, Vivekanand

Thumbnail for An Elementary Theory of Layout Wirability
An Elementary Theory of Layout Wirability
Lipski, Witold, Jr.; Preparata, Franco P.

Thumbnail for Automatic Generation of Instruction Sequences for Testing Microprocessors
Automatic Generation of Instruction Sequences for Testing Microprocessors
Lee, Jaushin; Patel, Janak H.

Thumbnail for State Justification Using Genetic Algorithms in Sequential Circuit Test Generation
State Justification Using Genetic Algorithms in Sequential Circuit Test Generation
Rudnick, Elizabeth Marie; Patel, Janak H.

Thumbnail for Finite Element Analysis on a 3-Dimensional Mesh of Trees
Finite Element Analysis on a 3-Dimensional Mesh of Trees
Hornick, Scot W.; Preparata, Franco P.

Thumbnail for Algorithms for Minimizing Test Sets for CMOS VLSI Circuits
Algorithms for Minimizing Test Sets for CMOS VLSI Circuits
Stancil, Charles Jay

Thumbnail for Automatic Test Generation for Bit-serial VLSI Digital Signal Processors
Automatic Test Generation for Bit-serial VLSI Digital Signal Processors
Roy, Rabindra Kumar

Thumbnail for Improved Algorithms for Cell Placement and Their Parallel Implementations
Improved Algorithms for Cell Placement and Their Parallel Implementations
Kim, Sungho

Thumbnail for The Design and Evaluation of a Novel Class of Reconfigurable Parallel Architectures
The Design and Evaluation of a Novel Class of Reconfigurable Parallel Architectures
Balasubramanian, Vijay

Thumbnail for Lower and Upper-Bounds for the General Junction Routing Problem
Lower and Upper-Bounds for the General Junction Routing Problem
Maddila, Sanjeev Rao; Zhou, Dian

Thumbnail for Design and Test of Bit-Serial Multiplier Arrays
Design and Test of Bit-Serial Multiplier Arrays
Scanlon, Joseph Thomas

Thumbnail for A Switch-Level Concurrent Fault Simulator for MOS Circuits
A Switch-Level Concurrent Fault Simulator for MOS Circuits
Lee, Terry Ping-Chung