University of Illinois Urbana-Champaign

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Showing 1–30 of 205 items
Thumbnail for A Brief Description of the NMP ISA and Benchmarks
A Brief Description of the NMP ISA and Benchmarks
Wei, Mingliang; Snir, Marc; Torrellas, Josep; Tremaine, R. Brett

Thumbnail for A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads
A Near-Memory Processor for Vector, Streaming and Bit Manipulation Workloads
Wei, Mingliang; Snir, Marc; Torrellas, Josep; Tremaine, R. Brett

Thumbnail for Sphinx Parallelization
Sphinx Parallelization
Tuck, James M.; Baugh, Lee W.; Renau, Jose; Torrellas, Josep

Thumbnail for A Microarchitectural Model of Process Variation for Near-threshold Computing
A Microarchitectural Model of Process Variation for Near-threshold Computing
Karpuzcu, Ulya R; Kolluru, Krishna; Kim, Nam Sung; Torrellas, Josep

Thumbnail for SpanCoverage: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
SpanCoverage: Architectural Support for Increasing the Path Coverage of Dynamic Bug Detection
Lu, Shan; Zhou, Pin; Liu, Wei; Zhou, YuanYuan; Torrellas, Josep

Thumbnail for Reducing Cache Misses in Numerical Applications Using Data Relocation and Prefetching
Reducing Cache Misses in Numerical Applications Using Data Relocation and Prefetching
Yamada, Yoji; Johnson, Teresa L.; Haab, Grant E.; Gyllenhaal, John C.; Hwu, Wen-Mei W.; Torrellas, Josep

Thumbnail for μComplexity: Estimating Processor Design Effort
μComplexity: Estimating Processor Design Effort
Bazeghi, Cyrus; Mesa-Martinez, Fracisco J.; Greskamp, Brian; Torrellas, Josep; Renau, Jose

Thumbnail for CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction
Ceze, Luis H.; Strauss, Karin; Tuck, James M.; Renau, Jose; Torrellas, Josep

Thumbnail for Managing Many-Core Aging
Managing Many-Core Aging
Karpuzcu, Rahmet U.

Thumbnail for High -Throughput Coherence Controllers
High -Throughput Coherence Controllers
Nguyen, Anthony-Trung Dinh

Thumbnail for On-chip wireless manycore architectures
On-chip wireless manycore architectures
Franques Garcia, Antonio Maria