University of Illinois Urbana-Champaign

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Showing 31–60 of 227 items
Thumbnail for Algorithms for VLSI Routing
Algorithms for VLSI Routing
Zhou, Dian

Thumbnail for Dynamic Fault Collapsing in Fault Simulation
Dynamic Fault Collapsing in Fault Simulation
Chandra, Susheel Jagdish

Thumbnail for Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Mui, Paul Chunhei

Thumbnail for Development of an Automatic Test Pattern Generation Package
Development of an Automatic Test Pattern Generation Package
Patel, Sanjaykumar Thakorbhai

Thumbnail for The Design and Simulation of a Fault-Tolerant Interconnection Network for Multiprocessor Systems
The Design and Simulation of a Fault-Tolerant Interconnection Network for Multiprocessor Systems
Dugar, Abhijeet

Thumbnail for Functional Testing of Microprocessors
Functional Testing of Microprocessors
Brahme, Dhananjay S.

Thumbnail for The Design and Evaluation of a Novel Class of Reconfigurable Parallel Architectures
The Design and Evaluation of a Novel Class of Reconfigurable Parallel Architectures
Balasubramanian, Vijay

Thumbnail for Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Saab, Daniel Georges

Thumbnail for ICs : The Driver for Information Technology
ICs : The Driver for Information Technology
Feng, Milton; Shanbhag, Naresh; Chiu, Yun; Chen, Deming; Rosenbaum, Elyse; Wong, Martin

Thumbnail for The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
Rogers, William Arthur

Thumbnail for Parallel Testing for Pattern Sensitive Faults in Semiconductor Random Access Memory
Parallel Testing for Pattern Sensitive Faults in Semiconductor Random Access Memory
Mazumder, Pinaki; Patel, Janak H.

Thumbnail for Totally Self-checking Circuits and Testable CMOS Circuits
Totally Self-checking Circuits and Testable CMOS Circuits
Jha, Niraj Kumar

Thumbnail for Logic and Fault Simulation of VLSI Circuits Including Hierarchical Techniques
Logic and Fault Simulation of VLSI Circuits Including Hierarchical Techniques
Saab, Daniel Georges

Thumbnail for Efficient Parallel Circuits and Algorithms for Division
Efficient Parallel Circuits and Algorithms for Division
Shankar, Narayan; Ramachandran, Vijaya

Thumbnail for Fast Logic Implication Discovery
Fast Logic Implication Discovery
Newquist, Jeffrey Aaron

Thumbnail for Use of High-level Descriptions in Fault Simulation and Test Generation
Use of High-level Descriptions in Fault Simulation and Test Generation
Chang, Hong-Tao Paul

Thumbnail for Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Pandey, Amit Raj

Thumbnail for New Algorithms for Sequential Diagnosis
New Algorithms for Sequential Diagnosis
Khanna, Sanjeev

Thumbnail for Measurement-Based Performance Models of Numerical Problems on Loosely Coupled Systems
Measurement-Based Performance Models of Numerical Problems on Loosely Coupled Systems
Rahmeh, Joseph Toufic

Thumbnail for Crosstalk Noise in Deep Submicron Integrated Circuit Design
Crosstalk Noise in Deep Submicron Integrated Circuit Design
Becer, Murat R.

Thumbnail for Graph Bisectioning and Related Problems
Graph Bisectioning and Related Problems
Saab, Youssef Georges

Thumbnail for Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Kriplani, Harish

Thumbnail for Design, Diagnosis and Reconfiguration of Defect-Tolerant VLSI
Design, Diagnosis and Reconfiguration of Defect-Tolerant VLSI
Chang, Ming-Feng

Thumbnail for Hierarchical Approaches to VLSI Circuit Layout
Hierarchical Approaches to VLSI Circuit Layout
Sarrafzadeh, Majid

Thumbnail for A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
Lim, Chieng-Fai

Thumbnail for Delay Fault Testing for Enhanced Full Scan Based Circuits
Delay Fault Testing for Enhanced Full Scan Based Circuits
Sharma, Manish

Thumbnail for Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Shah, Mihir Atul

Thumbnail for iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
Gee, Perry

Thumbnail for A New Control Structure for Serially Organized Memories in an Interactive Computer System
A New Control Structure for Serially Organized Memories in an Interactive Computer System
Tucker, Paul Thomas

Thumbnail for Angle-resolved photoemission studies of quantum-electronic coherence in metallic thin-film systems
Angle-resolved photoemission studies of quantum-electronic coherence in metallic thin-film systems
Brinkley, Matthew K.