University of Illinois Urbana-Champaign

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Showing 31–58 of 58 items
Thumbnail for Logic and layout optimizaton for sequential circuits
Logic and layout optimizaton for sequential circuits
Pan, Peichen

Thumbnail for Algorithms for VLSI Layout
Algorithms for VLSI Layout
Tollis, Ioannis Georgios

Thumbnail for Automatic layout synthesis for high-performance full custom VLSI chips
Automatic layout synthesis for high-performance full custom VLSI chips
Kim, Jaewon

Thumbnail for VLSI routing on the hexagonal grid
VLSI routing on the hexagonal grid
Powers, Kris Dee

Thumbnail for High-Level Resource Binding and Allocation for Power and Performance Optimization
High-Level Resource Binding and Allocation for Power and Performance Optimization
Cromar, Scott A.

Thumbnail for VLSI Routing on the Hexagonal Grid
VLSI Routing on the Hexagonal Grid
Powers, Kris Dee

Thumbnail for Index to Library Trends Volume 61
Index to Library Trends Volume 61
Carson, Justine

Thumbnail for Algorithmic results on physical design problems in VLSI and FPGA
Algorithmic results on physical design problems in VLSI and FPGA
Sun, Yachyang

Thumbnail for The Communication Complexity of Distributed Computing and a Parallel Algorithm for Polynomial Roots
The Communication Complexity of Distributed Computing and a Parallel Algorithm for Polynomial Roots
Tiwari, Prasoon

Thumbnail for Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
Cheng, Lei

Thumbnail for The Communication Complexity of Distributed Computing and a Parallel Algorithm for Polynomial Roots
The Communication Complexity of Distributed Computing and a Parallel Algorithm for Polynomial Roots
Tiwari, Prasoon

Thumbnail for Routing Algorithms for High-Performance VLSI Packaging
Routing Algorithms for High-Performance VLSI Packaging
Ozdal, Muhammet Mustafa

Thumbnail for Improved Algorithms for High-Level Synthesis and Their Parallel Implementations
Improved Algorithms for High-Level Synthesis and Their Parallel Implementations
Prabhakaran, Pradeep Kumar

Thumbnail for Routing Algorithms for High-Performance VLSI Packaging
Routing Algorithms for High-Performance VLSI Packaging
Ozdal, Muhammet Mustafa

Thumbnail for Task scheduling in high-level synthesis
Task scheduling in high-level synthesis
Park, Chaeryung

Thumbnail for Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
Novel CAD Techniques for New Challenges in Deep Sub-Micron VLSI Design
Cheng, Lei

Thumbnail for Improved Algorithms for High-level Synthesis and Their Parallel Implementations
Improved Algorithms for High-level Synthesis and Their Parallel Implementations
Prabhakaran, Pradeep Kumar

Thumbnail for Timing-constrained layout algorithms for symmetrical field-programmable gate arrays
Timing-constrained layout algorithms for symmetrical field-programmable gate arrays
Raman, Srilata

Thumbnail for Dynamic Data Structures for Two Dimensional Searching
Dynamic Data Structures for Two Dimensional Searching
Tamassia, Roberto

Thumbnail for Algorithms for VLSI Layout
Algorithms for VLSI Layout
Tollis, Ioannis Georgios

Thumbnail for Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology
Low-Power High-Performance Dynamic Circuit Design for Ultra-Deep Submicron Technology
Jung, Seong-Ook

Thumbnail for New Strategies for High Performance VLSI Physical Design
New Strategies for High Performance VLSI Physical Design
Xiang, Hua

Thumbnail for New Strategies for High Performance VLSI Physical Design
New Strategies for High Performance VLSI Physical Design
Xiang, Hua

Thumbnail for Reliable Low -Power Solution for High -Performance VLSI Circuit Design
Reliable Low -Power Solution for High -Performance VLSI Circuit Design
Kim, Ki Wook

Thumbnail for Matching on -Chip Data Storage to Telecommunication and Media Application Properties
Matching on -Chip Data Storage to Telecommunication and Media Application Properties
Hunter, Hillery Catriona

Thumbnail for Optimizing whole programs for code size
Optimizing whole programs for code size
Bartell, Sean

Thumbnail for Low-Power-Driven Synthesis Algorithms for Sequential and Combinational Circuits
Low-Power-Driven Synthesis Algorithms for Sequential and Combinational Circuits
Roy, Sumit

Thumbnail for Biological degradation of soluble microbial products in a combined system of anaerobic packed-bed reactors and a down-flow hanging sponge reactor
Biological degradation of soluble microbial products in a combined system of anaerobic packed-bed reactors and a down-flow hanging sponge reactor
Kim, Na Kyung