University of Illinois Urbana-Champaign

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Showing 1–30 of 159 items
Thumbnail for Programmable cyber networks for critical infrastructure
Programmable cyber networks for critical infrastructure
Kumar, Rakesh

Thumbnail for A measurement study of 802.11n links on commodity hardware
A measurement study of 802.11n links on commodity hardware
Kumar, Rakesh

Thumbnail for Proactive Peak Power Management for Many-Core Architectures
Proactive Peak Power Management for Many-Core Architectures
Sartori, John; Kumar, Rakesh

Thumbnail for Magellan: A Framework for Fast Multi-core Design Space Exploration and Optimization Using Search and Machine Learning
Magellan: A Framework for Fast Multi-core Design Space Exploration and Optimization Using Search and Machine Learning
Kang, Sukhun; Kumar, Rakesh

Thumbnail for Hardware/System Support for Four Economic Models for Many Core Computing
Hardware/System Support for Four Economic Models for Many Core Computing
Sloan, Joseph; Kumar, Rakesh

Thumbnail for A Study of Sampling-Based Hardware on Clustering Using Dirichlet Process Mixture Model
A Study of Sampling-Based Hardware on Clustering Using Dirichlet Process Mixture Model
Liu, Zuozhen

Thumbnail for Register Multimapping: Reducing Register Bank Conflicts Through One-to-Many Logical-to-Physical Register Mapping
Register Multimapping: Reducing Register Bank Conflicts Through One-to-Many Logical-to-Physical Register Mapping
Duong, Nam Le; Kumar, Rakesh

Thumbnail for MPreplay: Architecture Support for Deterministic Replay of Message Passing Programs on Message Passing Many-Core Processors
MPreplay: Architecture Support for Deterministic Replay of Message Passing Programs on Message Passing Many-Core Processors
Erik-Svensson, Carl; Kesler, David; Kumar, Rakesh; Pokam, Gilles

Thumbnail for The Case for Message Passing on Many-Core Chips
The Case for Message Passing on Many-Core Chips
Kumar, Rakesh; Mattson, Timothy G.; Pokam, Gilles; Van Der Wijngaart, Rob

Thumbnail for Reliability Models for Double Chipkill Detect/Correct Memory Systems
Reliability Models for Double Chipkill Detect/Correct Memory Systems
Jian, Xun; Blanchard, Sean; Debardeleben, Nathan; Sridharan, Vilas; Kumar, Rakesh

Thumbnail for A Hardware Implementation of Spike Sorting Using the Dirichlet Process Mixture Model
A Hardware Implementation of Spike Sorting Using the Dirichlet Process Mixture Model
Ma, Li

Thumbnail for Algorithmic approaches to enhancing and exploiting application-level error tolerance
Algorithmic approaches to enhancing and exploiting application-level error tolerance
Sloan, Joseph

Thumbnail for Programmable stochastic processors
Programmable stochastic processors
Sartori, John

Thumbnail for Network-on-chip design for a chiplet-based waferscale processor
Network-on-chip design for a chiplet-based waferscale processor
Cebry, Nicholas

Thumbnail for A numerical optimization-based methodology for application robustification: transforming applications for error tolerance
A numerical optimization-based methodology for application robustification: transforming applications for error tolerance
Sloan, Joseph A.

Thumbnail for On fault tolerance of hardware samplers
On fault tolerance of hardware samplers
Deka, Biplab

Thumbnail for A hardware acceleration technique for gradient descent and conjugate gradient
A hardware acceleration technique for gradient descent and conjugate gradient
Kesler, David R.

Thumbnail for Exploiting application level error resilience via deferred execution
Exploiting application level error resilience via deferred execution
Duwe, Henry

Thumbnail for BROAD: bold and reliable online approximate computing framework for diverse applications
BROAD: bold and reliable online approximate computing framework for diverse applications
Zhong, Liulin

Thumbnail for Performance analysis of machine learning applications on rapid: a highly parallel computer architecture
Performance analysis of machine learning applications on rapid: a highly parallel computer architecture
Modi, Aakash Ketan

Thumbnail for K-hot pipelining
K-hot pipelining
Lu, Dao

Thumbnail for Dependable design for low-cost ultra-low-power processors
Dependable design for low-cost ultra-low-power processors
Duwe III, Henry John

Thumbnail for Optimal power/performance pipelining for error resilient processors
Optimal power/performance pipelining for error resilient processors
Zea, Nicolas

Thumbnail for Architectural exploration of Si-IF many-die processors
Architectural exploration of Si-IF many-die processors
Petrisko, Daniel

Thumbnail for Adaptive reliability chipkill correct (ARCC)
Adaptive reliability chipkill correct (ARCC)
Jian, Xun

Thumbnail for Testing infrastructure and other considerations in a waferscale processor
Testing infrastructure and other considerations in a waferscale processor
Liu, Jingyang

Thumbnail for Inductive noise characterization and mitigation techniques for modern computer systems
Inductive noise characterization and mitigation techniques for modern computer systems
Smith, Andrew Timothy

Thumbnail for Common-case optimized memory hierarchy for data centers and HPC systems
Common-case optimized memory hierarchy for data centers and HPC systems
Jian, Xun

Thumbnail for Energy-efficient wireline transceivers
Energy-efficient wireline transceivers
Shu, Guanghua

Thumbnail for Specialization without complexity in heterogeneous memory systems
Specialization without complexity in heterogeneous memory systems
Alsop, Johnathan R.