University of Illinois Urbana-Champaign

Academic Unit
Collection
Author(s)
Keyword(s)
Type of Resource
Showing 1–30 of 385 items
Thumbnail for Exploration of GPU acceleration of K-mer counting (KMC2) and error correction tool (BLESS)
Exploration of GPU acceleration of K-mer counting (KMC2) and error correction tool (BLESS)
Li, Huiren

Thumbnail for Fcuda Memory Subsystems
Fcuda Memory Subsystems
Xu, Shuotao

Thumbnail for Hardware Acceleration of Short Read Alignment
Hardware Acceleration of Short Read Alignment
Chen, Daniel

Thumbnail for Sentinel Prime--A Novel Approach to 3D Classification
Sentinel Prime--A Novel Approach to 3D Classification
Mohamed, Harris

Thumbnail for An Implementation of a Human Position Recognition System on FPGA
An Implementation of a Human Position Recognition System on FPGA
Yu, Yangyang

Thumbnail for Graph sparsification on deep neural network
Graph sparsification on deep neural network
Qiu, Yijia

Thumbnail for LSMT for T-DLA+: Efficient computation of quantized LSMT networks
LSMT for T-DLA+: Efficient computation of quantized LSMT networks
Harisrikanth, Keshav

Thumbnail for Exploration of GPU acceleration for pair-HMM algorithm and its application in the DNA alignment problem
Exploration of GPU acceleration for pair-HMM algorithm and its application in the DNA alignment problem
Li, Enliang

Thumbnail for Exploration into rare sound detection using LSTM-RNN
Exploration into rare sound detection using LSTM-RNN
Chen, Yikuan

Thumbnail for A Method for Implementing Low Power Synchronization in a Wireless Sensor Network
A Method for Implementing Low Power Synchronization in a Wireless Sensor Network
Huang, Wenxun

Thumbnail for Verification of SoC Design Using Hardware-Software Co-Simulation with High-Level Synthesis
Verification of SoC Design Using Hardware-Software Co-Simulation with High-Level Synthesis
He, Leon

Thumbnail for Modeling and Design Space Exploration for Memory Hierarchy
Modeling and Design Space Exploration for Memory Hierarchy
Umenthum, Kenny

Thumbnail for FPGA-based SSD Emulation
FPGA-based SSD Emulation
Yu, Luyang

Thumbnail for Optimization methods for synthesizable IP instantiation in HLS tool
Optimization methods for synthesizable IP instantiation in HLS tool
Li, George

Thumbnail for An exploration into the effect of thresholding feature maps of convolutional neural network in frequency domain
An exploration into the effect of thresholding feature maps of convolutional neural network in frequency domain
Yu, Mang

Thumbnail for Depth Video Enhancement on FPGAS
Depth Video Enhancement on FPGAS
Ma, Sai

Thumbnail for A Method for Implementing Low Power Synchronization in a Wireless Sensor Network
A Method for Implementing Low Power Synchronization in a Wireless Sensor Network
Huang, Wenxun

Thumbnail for Gaussian Mixture Model Evaluation for Automatic Speech Recognition on GPU
Gaussian Mixture Model Evaluation for Automatic Speech Recognition on GPU
Nicklaus, Liana

Thumbnail for Evaluating the performance of high-level synthesis tools across languages: A case study on convolutional neural network on FPGA
Evaluating the performance of high-level synthesis tools across languages: A case study on convolutional neural network on FPGA
Kim, Dae Hee

Thumbnail for Extended HLS with high-level descriptive language for configurable algorithm-level spatial structure design
Extended HLS with high-level descriptive language for configurable algorithm-level spatial structure design
Wang, Chengyue

Thumbnail for Power Estimation for 3D NEM FPGA
Power Estimation for 3D NEM FPGA
Wei, Chunan

Thumbnail for A method for faster non-unit stride convolution in deep neural networks
A method for faster non-unit stride convolution in deep neural networks
Pan, Junhao

Thumbnail for Statistical Temperature Profile with Preserved Dependence on Process Variations
Statistical Temperature Profile with Preserved Dependence on Process Variations
Rogachev, Artem

Thumbnail for FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization
FastYield: Variation-Aware, Layout-Driven Simultaneous Binding and Module Selection for Performance Yield Optimization
Lucas, Gregory; Cromar, Scott A.; Chen, Deming

Thumbnail for A hybrid compressed deep neural network implementation on FPGA to balance accuracy and latency
A hybrid compressed deep neural network implementation on FPGA to balance accuracy and latency
Jeong, Paul

Thumbnail for Implementing neural machine translator with bi-directional GRU and attention mechanism on FPGAS using HLS
Implementing neural machine translator with bi-directional GRU and attention mechanism on FPGAS using HLS
Li, Qin

Thumbnail for Development of the Feedback Controlled Indentation System for Assessing Risk of Pressure Ulcers
Development of the Feedback Controlled Indentation System for Assessing Risk of Pressure Ulcers
Zhuge, Chuanhao

Thumbnail for VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip
VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip
Akram, Shoaib; Cromar, Scott A.; Lucas, Gregory; Papakonstantinou, Alexandros; Chen, Deming

Thumbnail for FPGA-Targeted High-Level Binding Algorithm for Power and Area Reduction with Glitch-Estimation
FPGA-Targeted High-Level Binding Algorithm for Power and Area Reduction with Glitch-Estimation
Cromar, Scott A.; Chen, Deming; Lee, Jaeho

Thumbnail for ICs : The Driver for Information Technology
ICs : The Driver for Information Technology
Feng, Milton; Shanbhag, Naresh; Chiu, Yun; Chen, Deming; Rosenbaum, Elyse; Wong, Martin