University of Illinois Urbana-Champaign

Submit an Item
Browse
About

Title

Author(s)

Contributor(s)

Issue Date

From:

To:

Keyword(s)

Abstract

Series/Report Name or Number

Type of Resource

Permalink

Full Text

Academic Unit

College of Engineering 53
Dept. of Computer Science 48
Graduate Dissertations and Theses at Illinois 37
College of Liberal Arts and Sciences 6
Dept. of Spanish, Italian and Portuguese 6
Summary of Engineering Research (1957-2008) 3
Coordinated Science Laboratory 2

Collection

Graduate Dissertations and Theses at Illinois 37
Dissertations and Theses - Computer Science 29
Research and Tech Reports - Computer Science 19
Dissertations and Theses - Spanish, Italian and Portuguese 6
Summary of Engineering Research (2003-2008) 3
Report - Coordinated Science Laboratory 2

Author(s)

Baugh, Lee W. 3
Ceze, Luis H. 3
Lu, Shan 3
Strauss, Karin 3
Teodorescu, Mircea-Radu 3
Tiwari, Abhishek 3
University of Illinois at Urbana-Champaign. College of Engineering 3
Agarwal, Mayank 2
Dhar, Vikram 2
Frank, Matthew I. 2

Keyword(s)

Computer Science 16
computer science 7
Computer Architecture 4
Literature, Romance 4
Computer architecture 2
Debugging 2
Deterministic Replay 2
Multiprocessors 2
Reliability 2
Research and publications sponsored in the College of Engineering 2

Type of Resource

text 47
Thesis 3

↑ ↓

Showing 1–30 of 61 items

1 (current)
2
3

Thumbnail for Bulk Operation and Data Coloring for Multiprocessor Programmability

Bulk Operation and Data Coloring for Multiprocessor Programmability

Ceze, Luis H.

Thumbnail for Bulk Operation and Data Coloring for Multiprocessor Programmability

Bulk Operation and Data Coloring for Multiprocessor Programmability

Ceze, Luis H.

Thumbnail for CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction

CAVA: Hiding L2 Misses with Checkpoint-Assisted Value Prediction

Ceze, Luis H.; Strauss, Karin; Tuck, James M.; Renau, Jose; Torrellas, Josep

Thumbnail for Software and architecture support for the bulk multicore

Software and architecture support for the bulk multicore

Ahn, Daniel

Thumbnail for Effective architectural support for detecting concurrency bugs

Effective architectural support for detecting concurrency bugs

Muzahid, Abdullah

Thumbnail for Cache Coherence in Embedded-Ring Multiprocessors

Cache Coherence in Embedded-Ring Multiprocessors

Strauss, Karin

Thumbnail for Scalable and flexible bulk architecture

Scalable and flexible bulk architecture

Qian, Xuehai

Thumbnail for Cache Coherence in Embedded -Ring Multiprocessors

Cache Coherence in Embedded -Ring Multiprocessors

Strauss, Karin

Thumbnail for Efficient Support for Speculative Tasking

Efficient Support for Speculative Tasking

Tuck, James M.

Thumbnail for Use of deterministic execution in testing and debugging of distributed software

Use of deterministic execution in testing and debugging of distributed software

Lin, Chia-Chi

Thumbnail for Techniques to detect and avert advanced software concurrency bugs

Techniques to detect and avert advanced software concurrency bugs

Qi, Shanxiang

Thumbnail for Efficient Support for Speculative Tasking

Efficient Support for Speculative Tasking

Tuck, James Murray, III

Thumbnail for Practical Time Travel of Multiprocessor Systems

Practical Time Travel of Multiprocessor Systems

Montesinos Ortego, Pablo

Thumbnail for Towards scalable and specialized application error analysis

Towards scalable and specialized application error analysis

Hassan N Mahmoud, Abdulrahman

Thumbnail for Improving failure diagnosis via better design and analysis of log messages

Improving failure diagnosis via better design and analysis of log messages

Yuan, Ding

Thumbnail for Understanding, Detecting and Exposing Concurrency Bugs

Understanding, Detecting and Exposing Concurrency Bugs

Lu, Shan

Thumbnail for Understanding, Detecting and Exposing Concurrency Bugs

Understanding, Detecting and Exposing Concurrency Bugs

Lu, Shan

Thumbnail for Understanding, Detecting and Exposing Concurrency Bugs

Understanding, Detecting and Exposing Concurrency Bugs

Lu, Shan

Thumbnail for Synchronizing Store Sets (SSS): Balancing the Benefits and Risks of Inter-thread Load Speculation

Synchronizing Store Sets (SSS): Balancing the Benefits and Risks of Inter-thread Load Speculation

Stone, Sam S.; Woley, Kevin M.; Malik, Kshitiz; Agarwal, Mayank; Dhar, Vikram; Frank, Matthew I.

Thumbnail for Making Parallel Programming Easy: Research Contributions from Illinois

Making Parallel Programming Easy: Research Contributions from Illinois

Submitter: David Padua

Thumbnail for Multilayer Techniques to Address Parameter Variation

Multilayer Techniques to Address Parameter Variation

Teodorescu, Mircea-Radu

Thumbnail for Confidence Based Out-of-Order Renaming for Speculatively Multithreaded Processors

Confidence Based Out-of-Order Renaming for Speculatively Multithreaded Processors

Malik, Kshitiz; Woley, Kevin M.; Stone, Samuel S.; Agarwal, Mayank; Dhar, Vikram; Frank, Matthew I.

Thumbnail for Transactional Programmability and Performance

Transactional Programmability and Performance

Baugh, Lee W.

Thumbnail for Transactional Programmability and Performance

Transactional Programmability and Performance

Baugh, Lee W.

Thumbnail for Transactional Programmability and Performance

Transactional Programmability and Performance

Baugh, Lee W.

Thumbnail for Maximal Causal Models for Sequentially Consistent Systems

Maximal Causal Models for Sequentially Consistent Systems

Șerbănuță, Traian Florin; Chen, Feng; Rosu, Grigore

Thumbnail for Multilayer Techniques to Address Parameter Variation

Multilayer Techniques to Address Parameter Variation

Teodorescu, Mircea-Radu

Thumbnail for An effect system and language for deterministic-by-default parallel programming

An effect system and language for deterministic-by-default parallel programming

Bocchino, Robert L., Jr.

Thumbnail for Verification and Performance of the DeNovo cache coherence protocol

Verification and Performance of the DeNovo cache coherence protocol

Komuravelli, Rakesh

Thumbnail for Multilayer Techniques to Address Parameter Variation

Multilayer Techniques to Address Parameter Variation

Teodorescu, Mircea-Radu

1 (current)
2
3

Contact us for questions and to provide feedback.

Your Name (optional)

Your Email (optional)

Your Comment

What is 6 + 1?

© 2023 University of Illinois Board of Trustees

Log In

I don't have an Illinois NetID

Use this login method if you don't have an @illinois.edu email address. (Oops, I do have one)

IDEALS migrated to a new platform on June 23, 2022. If you created your account prior to this date, you will have to reset your password using the forgot-password link below.

Email

Password

(I forgot my password)