University of Illinois Urbana-Champaign

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Showing 1–30 of 757 items
Thumbnail for Some Effects of Sampling on Geometric Properties of Linear Systems
Some Effects of Sampling on Geometric Properties of Linear Systems
Shor, Molly Hathaway

Thumbnail for The Design of a VLSI Systolic Array Processor Cell with Concurrent Error Detection
The Design of a VLSI Systolic Array Processor Cell with Concurrent Error Detection
Chin, Michael Tsung Sheng

Thumbnail for Knowledge-based testing of VLSI circuits
Knowledge-based testing of VLSI circuits
Brahme, Dhananjay S.

Thumbnail for Illinois Technograph v. 099, iss. 5 Apr. 1984
Illinois Technograph v. 099, iss. 5 Apr. 1984
Submitter: Sarah Shreeves

Thumbnail for The Mesh of Trees Architecture for Parallel Computation
The Mesh of Trees Architecture for Parallel Computation
Hornick, Scot Wayne

Thumbnail for Functional models for MOS VLSI circuits
Functional models for MOS VLSI circuits
Wehbeh, Jalal Anis

Thumbnail for A New CAD Design Framework
A New CAD Design Framework
Jiau, Hewijin

Thumbnail for Fault-Sensitivity and Wear-Out Analysis of VLSI Systems
Fault-Sensitivity and Wear-Out Analysis of VLSI Systems
Choi, Gwan Seung

Thumbnail for Parallel Processing for VLSI CAD Applications a Tutorial
Parallel Processing for VLSI CAD Applications a Tutorial
Banerjee, Prith

Thumbnail for The Retiming and Routing of VLSI Circuits
The Retiming and Routing of VLSI Circuits
Saxena, Prashant

Thumbnail for High-Level Power Estimation
High-Level Power Estimation
Nemani, Mahadevamurty

Thumbnail for A Critique and an Appraisal of VLSI Models of Computation
A Critique and an Appraisal of VLSI Models of Computation
Bilardi, G.; Pracchi, M.; Preparata, F.P.

Thumbnail for Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits
Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits
Bobba, Sudhakar

Thumbnail for Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability
Modeling and simulation of hot-carrier induced device and circuit degradation for VLSI reliability
Leblebici, Yusuf

Thumbnail for Structure and epitaxy studies of cobalt silicide/silicon heterostructures
Structure and epitaxy studies of cobalt silicide/silicon heterostructures
Zaluzec, Matthew John

Thumbnail for A simulation and redesign system for circuit hot-carrier reliability
A simulation and redesign system for circuit hot-carrier reliability
Li, Ping-Chung

Thumbnail for Estimating Power Dissipation in VLSI Circuits
Estimating Power Dissipation in VLSI Circuits
Najm, Farid N.

Thumbnail for The mesh of trees architecture for parallel computation
The mesh of trees architecture for parallel computation
Hornick, Scot W.

Thumbnail for Design automation for high performance complementary metal oxide-semiconductor VLSI circuits
Design automation for high performance complementary metal oxide-semiconductor VLSI circuits
Chen, Hau-Yung

Thumbnail for Timing and Area Optimization for VLSI Circuit and Layout
Timing and Area Optimization for VLSI Circuit and Layout
Chuang, Weitong

Thumbnail for A Simulation and Redesign System for Circuit Hot-Carrier Reliability
A Simulation and Redesign System for Circuit Hot-Carrier Reliability
Li, Ping-Chung

Thumbnail for Concurrent Error Detection in Vlsi Systems Through Structure Encoding (Fault Tolerance, Self-Checking)
Concurrent Error Detection in Vlsi Systems Through Structure Encoding (Fault Tolerance, Self-Checking)
Fuchs, W. Kent

Thumbnail for A framework for behavioral synthesis from partial design structures
A framework for behavioral synthesis from partial design structures
Dutt, Nikil D.

Thumbnail for Automatic Random Logic Layout Synthesis - a Module Generator Approach (Vlsi, Silicon Compilation, Design Automation, Cell Synthesis, Grid)
Automatic Random Logic Layout Synthesis - a Module Generator Approach (Vlsi, Silicon Compilation, Design Automation, Cell Synthesis, Grid)
Yu, Meng-Lin

Thumbnail for Statistical design of MOS VLSI circuits with designed experiments
Statistical design of MOS VLSI circuits with designed experiments
Yu, Tat Kwan Edgar

Thumbnail for An Optimum Channel Routing Algorithm in the Restricted Wire Overlap Model
An Optimum Channel Routing Algorithm in the Restricted Wire Overlap Model
Zhou, Dian

Thumbnail for A unified approach for assessing circuit and packaging technologies in a system environment
A unified approach for assessing circuit and packaging technologies in a system environment
Gura, Carol V.

Thumbnail for Parallel processing for VLSI simulation
Parallel processing for VLSI simulation
Mueller-Thuns, Robert Bernard

Thumbnail for Algorithms for VLSI Layout
Algorithms for VLSI Layout
Tollis, Ioannis Georgios

Thumbnail for Algorithms for VLSI routing
Algorithms for VLSI routing
Zhou, Dian