University of Illinois Urbana-Champaign

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Showing 91–120 of 1,930 items
Thumbnail for Totally Self-checking Circuits and Testable CMOS Circuits
Totally Self-checking Circuits and Testable CMOS Circuits
Jha, Niraj Kumar

Thumbnail for Compact Channel-Routing of Multiterminal Nets
Compact Channel-Routing of Multiterminal Nets
Sarrafzadeh, M.; Preparata, F.P.

Thumbnail for Functional Models for MOS VLSI Circuits
Functional Models for MOS VLSI Circuits
Wehbeh, Jalal Anis

Thumbnail for Crosstalk Noise and Timing Analysis of Digital VLSI Circuits with Coupled Interconnects
Crosstalk Noise and Timing Analysis of Digital VLSI Circuits with Coupled Interconnects
Lu, Ninglong

Thumbnail for Efficient Parallel Circuits and Algorithms for Division
Efficient Parallel Circuits and Algorithms for Division
Shankar, Narayan; Ramachandran, Vijaya

Thumbnail for Tradeoffs in Designing Accelerator Architectures for Visual Computing
Tradeoffs in Designing Accelerator Architectures for Visual Computing
Mahesri, Aqeel; Johnson, Daniel; Crago, Neal; Patel, Sanjay J.

Thumbnail for Partial Scan Beyond Cycle Cutting
Partial Scan Beyond Cycle Cutting
Saund, Gurjeet Singh

Thumbnail for Microassembly of a Silicon Micro-House
Microassembly of a Silicon Micro-House
Kahn, Alex Nathan

Thumbnail for Crosstalk Simulation in Digital Sequential Circuits
Crosstalk Simulation in Digital Sequential Circuits
Bolte, Pauline Marie

Thumbnail for Techniques to Speedup Test Generation for VLSI Circuits
Techniques to Speedup Test Generation for VLSI Circuits
Chandra, Susheel Jagdish

Thumbnail for Diagnostic Test Set Evaluation and Enhancement
Diagnostic Test Set Evaluation and Enhancement
Hartanto, Ismed D. S.

Thumbnail for Physical Design of Testable VLSI
Physical Design of Testable VLSI
Levitt, Marc Elliot

Thumbnail for Design for Yield Enhancement and Reconfiguration in Large Area VLSI/WSI Architectures
Design for Yield Enhancement and Reconfiguration in Large Area VLSI/WSI Architectures
Kuo, Sy-Yen

Thumbnail for Parallel Algorithms for Standard Cell Placement Using Simulated Annealing
Parallel Algorithms for Standard Cell Placement Using Simulated Annealing
Chandy, John Attupurathu

Thumbnail for Fault Ordering in Sequential Automatic Test Pattern Generation
Fault Ordering in Sequential Automatic Test Pattern Generation
Heydinger, Scott Michael

Thumbnail for State Information-Based Solutions for Sequential Circuit Diagnosis and Testing
State Information-Based Solutions for Sequential Circuit Diagnosis and Testing
Boppana, Vamsi

Thumbnail for Testing and Fault-Tolerance Aspect of High Density VLSI Memory
Testing and Fault-Tolerance Aspect of High Density VLSI Memory
Mazumder, Pinaki

Thumbnail for New Algorithms for Sequential Diagnosis
New Algorithms for Sequential Diagnosis
Khanna, Sanjeev

Thumbnail for Measurement-Based Performance Models of Numerical Problems on Loosely Coupled Systems
Measurement-Based Performance Models of Numerical Problems on Loosely Coupled Systems
Rahmeh, Joseph Toufic

Thumbnail for Use of High-level Descriptions in Fault Simulation and Test Generation
Use of High-level Descriptions in Fault Simulation and Test Generation
Chang, Hong-Tao Paul

Thumbnail for High-Level Methodologies for Test Generation and Logic Simulation
High-Level Methodologies for Test Generation and Logic Simulation
Dave, Utpal Jagdish

Thumbnail for Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Pandey, Amit Raj

Thumbnail for Graph Bisectioning and Related Problems
Graph Bisectioning and Related Problems
Saab, Youssef Georges

Thumbnail for Novel Algorithms for Placement and Routing and Their Parallel Implementations
Novel Algorithms for Placement and Routing and Their Parallel Implementations
Xing, Zhaoyun

Thumbnail for Symbolic Techniques for VLSI Test and Diagnosis
Symbolic Techniques for VLSI Test and Diagnosis
Kubiak, Kenneth Edward

Thumbnail for Design, Diagnosis and Reconfiguration of Defect-Tolerant VLSI
Design, Diagnosis and Reconfiguration of Defect-Tolerant VLSI
Chang, Ming-Feng

Thumbnail for Timing Verification and Synthesis of Circuits for Delay Fault Testability
Timing Verification and Synthesis of Circuits for Delay Fault Testability
Roy, Kaushik

Thumbnail for Hierarchical Approaches to VLSI Circuit Layout
Hierarchical Approaches to VLSI Circuit Layout
Sarrafzadeh, Majid

Thumbnail for A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
Lim, Chieng-Fai

Thumbnail for Statistical Design of MOS VLSI Circuits with Designed Experiments
Statistical Design of MOS VLSI Circuits with Designed Experiments
Yu, Tat-Kwan Edgar