University of Illinois Urbana-Champaign

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Showing 1–30 of 1,005 items
Thumbnail for An Algebraic Approach to Switch-Level Simulation
An Algebraic Approach to Switch-Level Simulation
Hajj, Ibrahim N.

Thumbnail for Circuit Simulation of Large Emitter-Coupled Logic Circuits
Circuit Simulation of Large Emitter-Coupled Logic Circuits
Brauer, Elizabeth Jewel

Thumbnail for Built-In Tests for VLSI Finite-State Machines
Built-In Tests for VLSI Finite-State Machines
Hua, Kien Anh

Thumbnail for Static Logic Implication with Application to Untestable Fault Identification
Static Logic Implication with Application to Untestable Fault Identification
Zhao, Jian-Kun

Thumbnail for Code Coverage Analysis for Behavioral Verilog Models
Code Coverage Analysis for Behavioral Verilog Models
Ma, Xiaojun

Thumbnail for Algorithm Based Fault Detection Techniques for Specific Applications
Algorithm Based Fault Detection Techniques for Specific Applications
Annapareddy, Narasimha Reddy L.

Thumbnail for Placement by Simulated Evolution
Placement by Simulated Evolution
Kling, Ralph Michael

Thumbnail for Enhancing Testability of VLSI Circuits Using Partial Reset Techniques
Enhancing Testability of VLSI Circuits Using Partial Reset Techniques
Mathew, Ben

Thumbnail for Automatic Bias Generation for Biased Random Instruction Generation
Automatic Bias Generation for Biased Random Instruction Generation
Bose, Mrinal

Thumbnail for Algorithms for VLSI Layout
Algorithms for VLSI Layout
Tollis, Ioannis Georgios

Thumbnail for High-Level Testability Analysis and Enhancement for Digital Systems
High-Level Testability Analysis and Enhancement for Digital Systems
Hsu, Frank Fu-Chang

Thumbnail for A High Level Approach to Test Generation for VLSI Circuits
A High Level Approach to Test Generation for VLSI Circuits
Narain, Prakash

Thumbnail for Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Hamzaoglu, Ilker

Thumbnail for Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests
Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests
Sharma, Manish

Thumbnail for Wrap: An Algorithm for Hierarchical Compression of Fault Simulation Primitives
Wrap: An Algorithm for Hierarchical Compression of Fault Simulation Primitives
Guzolek, John Francis

Thumbnail for Testing and Error Detection in Iterative Logic Arrays
Testing and Error Detection in Iterative Logic Arrays
Cheng, Wu-Tung

Thumbnail for Low-Power-Driven Synthesis Algorithms for Sequential and Combinational Circuits
Low-Power-Driven Synthesis Algorithms for Sequential and Combinational Circuits
Roy, Sumit

Thumbnail for Parallel Algorithms for Logic Synthesis
Parallel Algorithms for Logic Synthesis
De, Kaushik

Thumbnail for New Techniques to Verify Timing Correctness of Integrated Circuits
New Techniques to Verify Timing Correctness of Integrated Circuits
Heragu, Keerthinarayan Prasanna

Thumbnail for Performance Evaluation of Multiple Register Set Architectures and Cache Memories
Performance Evaluation of Multiple Register Set Architectures and Cache Memories
Eickemeyer, Richard James

Thumbnail for Optimization by Simulated Evolution and Its Application to Cell Placement
Optimization by Simulated Evolution and Its Application to Cell Placement
Kling, Ralph Michael

Thumbnail for Fast Timing Simulation of MOS VLSI Circuits
Fast Timing Simulation of MOS VLSI Circuits
Overhauser, David Vincent

Thumbnail for Architectural Level Test Generation and Fault Simulation
Architectural Level Test Generation and Fault Simulation
Lee, Jaushin

Thumbnail for Techniques for Sequential Circuit Automatic Test Generation
Techniques for Sequential Circuit Automatic Test Generation
Niermann, Thomas Michael

Thumbnail for Resource Management for Distributed Memory Multicomputers
Resource Management for Distributed Memory Multicomputers
Baxter, Jeffrey John

Thumbnail for BETA: Behavioral Testability Analyzer and Its Applications to High-Level Test Generation and Synthesis for Testability
BETA: Behavioral Testability Analyzer and Its Applications to High-Level Test Generation and Synthesis for Testability
Chen, Chung-Hsing

Thumbnail for Negativing Invention
Negativing Invention
Sherkow, Jacob S.

Thumbnail for The u.s. Computer Industry: An Economic-Legal Analysis of Its Major Growth Factors
The u.s. Computer Industry: An Economic-Legal Analysis of Its Major Growth Factors
Soma, John Trygve

Thumbnail for Computer technology: A forecast for the future
Computer technology: A forecast for the future
Kubitz, William J.

Thumbnail for Illinois Technograph v. 098, iss. 5 Apr. 1983
Illinois Technograph v. 098, iss. 5 Apr. 1983
Submitter: Sarah Shreeves