University of Illinois Urbana-Champaign

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Showing 91–120 of 1,649 items
Thumbnail for Graph Bisectioning and Related Problems
Graph Bisectioning and Related Problems
Saab, Youssef Georges

Thumbnail for Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Symbolic Switch-Level Logic and Fault Simulation of MOS VLSI Circuits
Saab, Daniel Georges

Thumbnail for Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Mui, Paul Chunhei

Thumbnail for Functional Testing of Microprocessors
Functional Testing of Microprocessors
Brahme, Dhananjay S.

Thumbnail for The Design and Evaluation of a Novel Class of Reconfigurable Parallel Architectures
The Design and Evaluation of a Novel Class of Reconfigurable Parallel Architectures
Balasubramanian, Vijay

Thumbnail for Wrap: An Algorithm for Hierarchical Compression of Fault Simulation Primitives
Wrap: An Algorithm for Hierarchical Compression of Fault Simulation Primitives
Guzolek, John Francis

Thumbnail for The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
Rogers, William Arthur

Thumbnail for Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Shah, Mihir Atul

Thumbnail for Implication Graph Based Domino Logic Synthesis
Implication Graph Based Domino Logic Synthesis
Submitter: Michelle Self-Ballard

Thumbnail for Investigating the effectiveness of measurement-device-independent quantum key distribution with weak coherent pulses
Investigating the effectiveness of measurement-device-independent quantum key distribution with weak coherent pulses
Dugad, Annika

Thumbnail for Bottom-Up High-Level Current Macro-Models for Logic Blocks
Bottom-Up High-Level Current Macro-Models for Logic Blocks
Bodapati, Srinivas

Thumbnail for An Eigenvalue-Based Approach to the Finite Time Behavior of Simulated Annealling
An Eigenvalue-Based Approach to the Finite Time Behavior of Simulated Annealling
Desai, Madhav Pandurang

Thumbnail for Early Power Estimation for VLSI Circuits
Early Power Estimation for VLSI Circuits
Büyükşahin, Kavel M.

Thumbnail for Resource Management for Distributed Memory Multicomputers
Resource Management for Distributed Memory Multicomputers
Baxter, Jeffrey John

Thumbnail for ICs : The Driver for Information Technology
ICs : The Driver for Information Technology
Feng, Milton; Shanbhag, Naresh; Chiu, Yun; Chen, Deming; Rosenbaum, Elyse; Wong, Martin

Thumbnail for On the Tunability of a High-Level Area Model
On the Tunability of a High-Level Area Model
Büyükşahin, Kavel M.; Najm, Farid N.

Thumbnail for A Comparative Study of Duobinary and NRZ Modulation for High-Speed I/O
A Comparative Study of Duobinary and NRZ Modulation for High-Speed I/O
Koh, Yee Lih

Thumbnail for Two-Level Hierarchical Coupling Aware Static Timing Simulation
Two-Level Hierarchical Coupling Aware Static Timing Simulation
Li, Ninglong; Hajj, Ibrahim N.

Thumbnail for Accurate Power Estimation for Large Sequential Circuits
Accurate Power Estimation for Large Sequential Circuits
Kozhaya, Joseph N.

Thumbnail for A Characterization of Separating Pairs and Triplets in a Graph
A Characterization of Separating Pairs and Triplets in a Graph
Kanevsky, Arkady; Ramachandran, Vijaya

Thumbnail for Improving the Accuracy of Krylov Subspace-based Order Reduction Algorithms
Improving the Accuracy of Krylov Subspace-based Order Reduction Algorithms
Becer, Murat; Lu, Ninglong; Hajj, Ibrahim N.

Thumbnail for Efficient Testing for Bridging Faults in Digital Integrated Circuits
Efficient Testing for Bridging Faults in Digital Integrated Circuits
Chen, Tzu-Hao

Thumbnail for Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests
Enhancing Defect Coverage of VLSI Chips by Using Cost Effective Delay Fault Tests
Sharma, Manish

Thumbnail for Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variations in the Power Distribution Network of VLSI Circuits
Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variations in the Power Distribution Network of VLSI Circuits
Bobba, Sudhakar

Thumbnail for Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Hamzaoglu, Ilker

Thumbnail for Totally Self-checking Circuits and Testable CMOS Circuits
Totally Self-checking Circuits and Testable CMOS Circuits
Jha, Niraj Kumar

Thumbnail for Fast Logic Implication Discovery
Fast Logic Implication Discovery
Newquist, Jeffrey Aaron

Thumbnail for Use of High-level Descriptions in Fault Simulation and Test Generation
Use of High-level Descriptions in Fault Simulation and Test Generation
Chang, Hong-Tao Paul

Thumbnail for Testing and Error Detection in Iterative Logic Arrays
Testing and Error Detection in Iterative Logic Arrays
Cheng, Wu-Tung

Thumbnail for Crosstalk Noise in Deep Submicron Integrated Circuit Design
Crosstalk Noise in Deep Submicron Integrated Circuit Design
Becer, Murat R.