University of Illinois Urbana-Champaign

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Showing 61–90 of 1,649 items
Thumbnail for Parallel Algorithms for Circuit Simulation
Parallel Algorithms for Circuit Simulation
Desai, Madhav Pandurang

Thumbnail for A Genetic-Algorithm Approach to Architectural-Level Justification of Precomputed Vectors
A Genetic-Algorithm Approach to Architectural-Level Justification of Precomputed Vectors
Hsiao, Michael S.; Patel, Janak H.

Thumbnail for Some NP-Complete Problems in the Physical Design of Digital Integrated Circuits
Some NP-Complete Problems in the Physical Design of Digital Integrated Circuits
Saab, Youssef Georges; Rao, Vasant B.

Thumbnail for Parallel-Concurrent Versus Concurrent Fault Simulation
Parallel-Concurrent Versus Concurrent Fault Simulation
Saab, Daniel Georges; Rahmeh, Joseph T.; Hajj, Ibrahim N.

Thumbnail for On the Convergence of Block Time-Point Relaxation Methods for Circuit Simulation
On the Convergence of Block Time-Point Relaxation Methods for Circuit Simulation
Desai, Madhav P.; Hajj, Ibrahim N.

Thumbnail for Reliability Driven Synthesis of Sequential Circuits
Reliability Driven Synthesis of Sequential Circuits
Hsu, Frank F.; Hsiao, Michael S.; Banerjee, Prithviraj

Thumbnail for Switch-Level Test Generation for MOS VLSI Circuits
Switch-Level Test Generation for MOS VLSI Circuits
Najm, Farid Nasri

Thumbnail for Automatic Generation of Instruction Sequences for Testing Microprocessors
Automatic Generation of Instruction Sequences for Testing Microprocessors
Lee, Jaushin; Patel, Janak H.

Thumbnail for A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
Lim, Chieng-Fai

Thumbnail for Delay Fault Testing for Enhanced Full Scan Based Circuits
Delay Fault Testing for Enhanced Full Scan Based Circuits
Sharma, Manish

Thumbnail for On the C-Testability of Generalized Counters
On the C-Testability of Generalized Counters
Chatterjee, Abhijit; Abraham, Jacob A.

Thumbnail for Parallel Testing for Pattern Sensitive Faults in Semiconductor Random Access Memory
Parallel Testing for Pattern Sensitive Faults in Semiconductor Random Access Memory
Mazumder, Pinaki; Patel, Janak H.

Thumbnail for State Justification Using Genetic Algorithms in Sequential Circuit Test Generation
State Justification Using Genetic Algorithms in Sequential Circuit Test Generation
Rudnick, Elizabeth Marie; Patel, Janak H.

Thumbnail for Test Generation and Evaluation for Bridging Faults in CMOS VLSI Circuits
Test Generation and Evaluation for Bridging Faults in CMOS VLSI Circuits
Lee, Terry Ping-Chung

Thumbnail for On the Convergence of Newton's Method for Solving Systems of Linear Equations
On the Convergence of Newton's Method for Solving Systems of Linear Equations
Hornick, Scot W.; Preparata, Franco P.; Tiwari, Prasoon

Thumbnail for Built-In Tests for VLSI Finite-State Machines
Built-In Tests for VLSI Finite-State Machines
Hua, Kien Anh

Thumbnail for Design and Implementation of an Actor Based Parallel VHDL Simulator
Design and Implementation of an Actor Based Parallel VHDL Simulator
Krishnaswamy, V.; Banerjee, P.

Thumbnail for Algorithms for Minimizing Test Sets for CMOS VLSI Circuits
Algorithms for Minimizing Test Sets for CMOS VLSI Circuits
Stancil, Charles Jay

Thumbnail for Dynamic Fault Collapsing in Fault Simulation
Dynamic Fault Collapsing in Fault Simulation
Chandra, Susheel Jagdish

Thumbnail for Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
Parallel Algorithms for Force Directed Scheduling of Flattened and Hierarchical Signal Flow Graphs
Prabhakaran, Pradeep; Banerjee, Prithviraj

Thumbnail for Algorithms for VLSI Routing
Algorithms for VLSI Routing
Zhou, Dian

Thumbnail for ProperCAD: A Portable Object-Oriented Parallel Environment for VLSI CAD
ProperCAD: A Portable Object-Oriented Parallel Environment for VLSI CAD
Ramkumar, Balkrishna; Banerjee, Prithviraj

Thumbnail for Parallel Architecture for Concurrent Fault Simulation
Parallel Architecture for Concurrent Fault Simulation
Stein, Andrew James

Thumbnail for Code Coverage Analysis for Behavioral Verilog Models
Code Coverage Analysis for Behavioral Verilog Models
Ma, Xiaojun

Thumbnail for The Design and Simulation of a Fault-Tolerant Interconnection Network for Multiprocessor Systems
The Design and Simulation of a Fault-Tolerant Interconnection Network for Multiprocessor Systems
Dugar, Abhijeet

Thumbnail for New Algorithms for Sequential Diagnosis
New Algorithms for Sequential Diagnosis
Khanna, Sanjeev

Thumbnail for Efficient Algorithms for the Channel Routing Problem
Efficient Algorithms for the Channel Routing Problem
Sarrafzadeh, Majid

Thumbnail for Automatic Bias Generation for Biased Random Instruction Generation
Automatic Bias Generation for Biased Random Instruction Generation
Bose, Mrinal

Thumbnail for Concurrent Simulation Techniques Exploiting Hierarchy
Concurrent Simulation Techniques Exploiting Hierarchy
Rogers, William Arthur

Thumbnail for Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Pandey, Amit Raj