University of Illinois Urbana-Champaign

Academic Unit
Collection
Author(s)
Keyword(s)
Type of Resource
Showing 841–870 of 27,356 items
Thumbnail for Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Test Time and Test Data Volume Reduction Techniques for VLSI Circuits
Pandey, Amit Raj

Thumbnail for Research Methods in Community Informatics at the Broadband Moment
Research Methods in Community Informatics at the Broadband Moment
Williams, Kate

Thumbnail for Reflective Database Access Control
Reflective Database Access Control
Olson, Lars E.

Thumbnail for Design for Yield Enhancement and Reconfiguration in Large Area VLSI/WSI Architectures
Design for Yield Enhancement and Reconfiguration in Large Area VLSI/WSI Architectures
Kuo, Sy-Yen

Thumbnail for Parallel Algorithms for Standard Cell Placement Using Simulated Annealing
Parallel Algorithms for Standard Cell Placement Using Simulated Annealing
Chandy, John Attupurathu

Thumbnail for Fault Ordering in Sequential Automatic Test Pattern Generation
Fault Ordering in Sequential Automatic Test Pattern Generation
Heydinger, Scott Michael

Thumbnail for State Information-Based Solutions for Sequential Circuit Diagnosis and Testing
State Information-Based Solutions for Sequential Circuit Diagnosis and Testing
Boppana, Vamsi

Thumbnail for Safety Implications of Robotic Surgery: A Study of 13 Years of FDA Data on da Vinci Surgical Systems
Safety Implications of Robotic Surgery: A Study of 13 Years of FDA Data on da Vinci Surgical Systems
Alemzadeh, Homa; Raman, Jai; Leveson, Nancy; Iyer, Ravishankar K.

Thumbnail for Microassembly of a Silicon Micro-House
Microassembly of a Silicon Micro-House
Kahn, Alex Nathan

Thumbnail for Design, Diagnosis and Reconfiguration of Defect-Tolerant VLSI
Design, Diagnosis and Reconfiguration of Defect-Tolerant VLSI
Chang, Ming-Feng

Thumbnail for Timing Verification and Synthesis of Circuits for Delay Fault Testability
Timing Verification and Synthesis of Circuits for Delay Fault Testability
Roy, Kaushik

Thumbnail for Hierarchical Approaches to VLSI Circuit Layout
Hierarchical Approaches to VLSI Circuit Layout
Sarrafzadeh, Majid

Thumbnail for A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
A Parallel Algorithm for Multi-Level Logic Synthesis Using the Transduction Method
Lim, Chieng-Fai

Thumbnail for Low cycle fatigue properties of ausformed steel
Low cycle fatigue properties of ausformed steel
Matheny, J.E., Jr.

Thumbnail for iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
iSITE: Automatic Circuit Synthesis for Double-Metal CMOS VLSI Circuits
Gee, Perry

Thumbnail for Switch-Level Timing Simulation of MOS VLSI Circuits
Switch-Level Timing Simulation of MOS VLSI Circuits
Rao, Vasant Bangalore

Thumbnail for Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
Parallel Algorithms for Sequential Circuit Fault Simulation and Test Generation
Krishnaswamy, Dilip

Thumbnail for Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Shah, Mihir Atul

Thumbnail for Analysis of Failures in Windows NT Systems
Analysis of Failures in Windows NT Systems
Kalyanakrishnan, Mahesh Chittur

Thumbnail for Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Smart, David William

Thumbnail for The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
The Use of Hierarchy in Test Generation, Fault Simulation, and Testability Analysis Algorithms
Rogers, William Arthur

Thumbnail for Estimating fatigue crack initiation and propagation lives in notched plates under variable loading histories
Estimating fatigue crack initiation and propagation lives in notched plates under variable loading histories
Socie, Darrell F.

Thumbnail for Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Worst Case Voltage Drops in Power and Ground Buses of CMOS VLSI Circuits
Kriplani, Harish

Thumbnail for Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Tejayadi, Ongky

Thumbnail for Design, Analysis and Reconfiguration of Defect-Tolerant VLSI and Parallel Processor Arrays
Design, Analysis and Reconfiguration of Defect-Tolerant VLSI and Parallel Processor Arrays
Shi, Weiping

Thumbnail for Investigation of the impacts of deploying reactors fueled by high-assay low enriched uranium
Investigation of the impacts of deploying reactors fueled by high-assay low enriched uranium
Bachmann, Amanda M • 2024

Thumbnail for Statistical Design of MOS VLSI Circuits with Designed Experiments
Statistical Design of MOS VLSI Circuits with Designed Experiments
Yu, Tat-Kwan Edgar

Thumbnail for Performance Aspects of Computers with Graphical User Interfaces
Performance Aspects of Computers with Graphical User Interfaces
Gupta, Aloke

Thumbnail for Delay Fault Testing for Enhanced Full Scan Based Circuits
Delay Fault Testing for Enhanced Full Scan Based Circuits
Sharma, Manish

Thumbnail for Statistical Error Compensation for Robust Digital Signal Processing and Machine Learning
Statistical Error Compensation for Robust Digital Signal Processing and Machine Learning
Kim, Eric Park