University of Illinois Urbana-Champaign

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Showing 751–780 of 27,356 items
Universal Parallel Computing Research Center
Thumbnail for Enhanced automatic generation control with uncertainty
Enhanced automatic generation control with uncertainty
Apostolopoulou, Dimitra

Thumbnail for High Level Test Generation Using Software Testing Metrics
High Level Test Generation Using Software Testing Metrics
Johnson, Mark Willard

Thumbnail for Maximum Switching Activity Estimation for CMOS VLSI Circuits
Maximum Switching Activity Estimation for CMOS VLSI Circuits
Bobba, Sudhakar

Thumbnail for Evaluation of a Reconfigurable Architecture for Adaptive Digital Beamforming Using the OODRA Workbench
Evaluation of a Reconfigurable Architecture for Adaptive Digital Beamforming Using the OODRA Workbench
Wernimont, Thomas Lawrence

Thumbnail for Algorithms for VLSI Routing
Algorithms for VLSI Routing
Zhou, Dian

OTCR Consulting
Thumbnail for Algorithms for Minimizing Test Sets for CMOS VLSI Circuits
Algorithms for Minimizing Test Sets for CMOS VLSI Circuits
Stancil, Charles Jay

Thumbnail for Dynamic Fault Collapsing in Fault Simulation
Dynamic Fault Collapsing in Fault Simulation
Chandra, Susheel Jagdish

Thumbnail for Reducing Cache Misses in Numerical Applications Using Data Relocation and Prefetching
Reducing Cache Misses in Numerical Applications Using Data Relocation and Prefetching
Yamada, Yoji; Johnson, Teresa L.; Haab, Grant E.; Gyllenhaal, John C.; Hwu, Wen-Mei W.; Torrellas, Josep

Thumbnail for The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
Chang, Pohua P.; Lavery, Daniel M.; Hwu, Wen-Mei W.

Thumbnail for Hierarchical Simulation of MOS Circuits Using Extracted Functional Models
Hierarchical Simulation of MOS Circuits Using Extracted Functional Models
Wehbeh, Jalal Anis

Thumbnail for CMOS Bridging Fault Simulation
CMOS Bridging Fault Simulation
Greenstein, Gary Stuart

Thumbnail for Sequential Circuit Test Generation Using Genetic Techniques
Sequential Circuit Test Generation Using Genetic Techniques
Hsiao, Michael Shaun

Thumbnail for Variable-Delay Event-Driven Logic and Fault Simulation
Variable-Delay Event-Driven Logic and Fault Simulation
Hsiao, Michael Shaun

Thumbnail for Parallel Algorithms for State Assignment of Finite State Machines
Parallel Algorithms for State Assignment of Finite State Machines
Hasteer, Gagan

Thumbnail for The Design and Simulation of a Fault-Tolerant Interconnection Network for Multiprocessor Systems
The Design and Simulation of a Fault-Tolerant Interconnection Network for Multiprocessor Systems
Dugar, Abhijeet

Thumbnail for Fault-Tolerant Computing: An Overview
Fault-Tolerant Computing: An Overview
Iyer, R.K.; Patel, J.H.; Fuchs, W.K.; Banerjee, P.; Horst, R.

Thumbnail for Three Essays in Empirical Asset Pricing
Three Essays in Empirical Asset Pricing
Jacobs, Thomas A.

Thumbnail for New Techniques for Probabilistic Simulation of VLSI CMOS Circuits
New Techniques for Probabilistic Simulation of VLSI CMOS Circuits
Stamoulis, Georgios I.

Thumbnail for Probabilistic Simulation for Reliability and Average Power Estimation
Probabilistic Simulation for Reliability and Average Power Estimation
Stamoulis, Georgios Ioannis

Thumbnail for Concurrent Simulation Techniques Exploiting Hierarchy
Concurrent Simulation Techniques Exploiting Hierarchy
Rogers, William Arthur

Thumbnail for The Design and Implementation of a Workbench for Application Specific Message-Passing Parallel Reconfigurable Architectures
The Design and Implementation of a Workbench for Application Specific Message-Passing Parallel Reconfigurable Architectures
Hwang, Kou-Rey David

Thumbnail for Demand for electricity: a case in South Korea
Demand for electricity: a case in South Korea
Liu, Tingwen

Thumbnail for Fault Dictionary Compaction Using Structural and Tree-Based Techniques
Fault Dictionary Compaction Using Structural and Tree-Based Techniques
Boppana, Vamsi

Thumbnail for Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Mui, Paul Chunhei

Thumbnail for The Mesh of Trees Architecture for Parallel Computation
The Mesh of Trees Architecture for Parallel Computation
Hornick, Scot Wayne

Thumbnail for Do Women Score Lower than Men on Computer Engineering Examinations?
Do Women Score Lower than Men on Computer Engineering Examinations?
Liao, I-Ju

Thumbnail for A Simulation and Redesign System for Circuit Hot-Carrier Reliability
A Simulation and Redesign System for Circuit Hot-Carrier Reliability
Li, Ping-Chung

Thumbnail for Improved Algorithms for Cell Placement and Their Parallel Implementations
Improved Algorithms for Cell Placement and Their Parallel Implementations
Kim, Sungho