University of Illinois Urbana-Champaign

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Showing 91–120 of 643 items
Thumbnail for Illinois Technograph v. 098-101 (1982-1986)
Illinois Technograph v. 098-101 (1982-1986)
Submitter: Timothy Donohue

Thumbnail for iSITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
iSITE: Automatic circuit synthesis for double-metal CMOS VLSI circuits
Gee, Perry

Thumbnail for The mesh of trees architecture for parallel computation
The mesh of trees architecture for parallel computation
Hornick, Scot W.

Thumbnail for Report on Workshop on High Performance Computing and Communications for Grand Challenge Applications: Computer Vision, Speech and Natural Language Processing, and Artificial Intelligence
Report on Workshop on High Performance Computing and Communications for Grand Challenge Applications: Computer Vision, Speech and Natural Language Processing, and Artificial Intelligence
Wah, Benjamin W.

Thumbnail for A Low-Overhead Coherence Solution for Bus-Organized Multiprocessors with Private Cache Memories
A Low-Overhead Coherence Solution for Bus-Organized Multiprocessors with Private Cache Memories
Papamarcos, Mark Stanley

Thumbnail for Architecture and CAD for nanoscale and 3d FPGA
Architecture and CAD for nanoscale and 3d FPGA
Dong, Chen

Thumbnail for Algorithms for VLSI Routing
Algorithms for VLSI Routing
Zhou, Dian

Thumbnail for Advances in parallel programming for electronic design automation
Advances in parallel programming for electronic design automation
Lin, Chun-Xun

Thumbnail for Circuit simulation models and optical switch structure for interconnection networks
Circuit simulation models and optical switch structure for interconnection networks
Gao, Siwei

Thumbnail for Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Tiwari, Abhishek

Thumbnail for Sufficient Conditions, Cost Bounds, and Approximation Algorithms for the Graph Bisectioning Problem
Sufficient Conditions, Cost Bounds, and Approximation Algorithms for the Graph Bisectioning Problem
Saab, Youssef Georges; Rao, Vasant B.

Thumbnail for Transient Error Recovery Techniques for Pipelines and Memory Systems
Transient Error Recovery Techniques for Pipelines and Memory Systems
Saleh, Abdallah Medhat

Thumbnail for The role of the library in an electronic society: Papers presented at the 1979 Clinic on Library Applications of Data Processing
The role of the library in an electronic society: Papers presented at the 1979 Clinic on Library Applications of Data Processing
Submitter: Sarah Shreeves

Thumbnail for SOI Circuit Design Styles and High-Level Circuit Modeling Techniques
SOI Circuit Design Styles and High-Level Circuit Modeling Techniques
Kanj, Rouwaida

Thumbnail for Techniques to Mitigate the Effects of Congenital Faults in Processors
Techniques to Mitigate the Effects of Congenital Faults in Processors
Sarangi, Smruti R.

Thumbnail for Modeling and Extraction of Interconnect Parameters in Very-Large-Scale Integrated Circuits
Modeling and Extraction of Interconnect Parameters in Very-Large-Scale Integrated Circuits
Yuan, Chen-Ping

Thumbnail for IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors
Chang, Pohua P.; Mahlke, Scott A.; Chen, William Y.; Warter, Nancy J.; Hwu, Wen-Mei W.

Thumbnail for Physical Design of Testable VLSI
Physical Design of Testable VLSI
Levitt, Marc Elliot

Thumbnail for An Intelligent Memory for Data -Parallel Applications
An Intelligent Memory for Data -Parallel Applications
Kang, Yi

Thumbnail for The Summary of Engineering Research 2003
The Summary of Engineering Research 2003
University of Illinois at Urbana-Champaign. College of Engineering

Thumbnail for Techniques to Mitigate the Effects of Congenital Faults in Processors
Techniques to Mitigate the Effects of Congenital Faults in Processors
Sarangi, Smruti R.

Thumbnail for Architecture and CAD for Nanoscale and Three-Dimensional FPGA
Architecture and CAD for Nanoscale and Three-Dimensional FPGA
Dong, Chen

Thumbnail for Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors
Tiwari, Abhishek

Thumbnail for Optimization by simulated evolution and its application to cell placement
Optimization by simulated evolution and its application to cell placement
Kling, Ralph Michael

Thumbnail for Cost Effective Soft Error Mitigation in Microprocessors
Cost Effective Soft Error Mitigation in Microprocessors
Wang, Nicholas J.

Thumbnail for The Summary of Engineering Research 2004
The Summary of Engineering Research 2004
University of Illinois at Urbana-Champaign. College of Engineering

Thumbnail for Efficient Instruction Sequencing with Inline Target Insertion
Efficient Instruction Sequencing with Inline Target Insertion
Hwu, Wen-Mei W.; Chang, Pohua P.

Thumbnail for Reconfiguration of Fault-Tolerant VLSI Systems
Reconfiguration of Fault-Tolerant VLSI Systems
Libeskind-Hadas, Ran

Thumbnail for Parallel algorithms for CAD with applications to circuit extraction
Parallel algorithms for CAD with applications to circuit extraction
Belkhale, Krishna P.

Thumbnail for Modeling and Extraction of Interconnect Parameters in Very-Large-Scale Integrated Circuits
Modeling and Extraction of Interconnect Parameters in Very-Large-Scale Integrated Circuits
Yuan, Chen-Ping