University of Illinois Urbana-Champaign

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Showing 211–240 of 643 items
Thumbnail for The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)
The Squeeze Algorithm for Pla Minimization (Logic, Computer-Aided, Circuit Design)
Krolikoski, Stanley Joseph

Thumbnail for System-level trace signal selection for post-silicon debug using linear programming
System-level trace signal selection for post-silicon debug using linear programming
Amrein, Matthew Curtis

Thumbnail for Design and Analysis of Fault-Tolerant Processor Arrays for Numerical Applications
Design and Analysis of Fault-Tolerant Processor Arrays for Numerical Applications
Chen, Chien-Yi

Thumbnail for Interconnection networks and data prefetching for large-scale multiprocessors: Design and performance
Interconnection networks and data prefetching for large-scale multiprocessors: Design and performance
Kim, Sun-il

Thumbnail for A Convex Programming Approach to Problems in VLSI Design
A Convex Programming Approach to Problems in VLSI Design
Sapatnekar, Sachin Suresh

Thumbnail for The Retiming and Routing of VLSI Circuits
The Retiming and Routing of VLSI Circuits
Saxena, Prashant

Thumbnail for Incremental circuit simulation and timing analysis techniques
Incremental circuit simulation and timing analysis techniques
Ju, Yun-Cheng

Thumbnail for FAMAS: Fault Modeling via Adaptive Simulation
FAMAS: Fault Modeling via Adaptive Simulation
Jin, Haiming

Thumbnail for Energy-efficient wireline transceivers
Energy-efficient wireline transceivers
Shu, Guanghua

Thumbnail for Performance Modeling and Enhancement of the Structured Memory Access Architecture
Performance Modeling and Enhancement of the Structured Memory Access Architecture
Kahhaleh, Bassam Zuhair

Thumbnail for VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip
VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip
Akram, Shoaib; Cromar, Scott A.; Lucas, Gregory; Papakonstantinou, Alexandros; Chen, Deming

Thumbnail for An enhancement/depletion process for III-V compound semiconductor heterostructure field-effect transistors and optoelectronic integrated circuits
An enhancement/depletion process for III-V compound semiconductor heterostructure field-effect transistors and optoelectronic integrated circuits
Tong, Minh Ho

Thumbnail for High quality functional coverage based trace signal selection for post-silicon validation
High quality functional coverage based trace signal selection for post-silicon validation
Ma, Sai

Thumbnail for Exploring nanoscale characterization of low dimensional electronic materials
Exploring nanoscale characterization of low dimensional electronic materials
Seabron, Eric M

Thumbnail for Two-Dimensional Analysis of Narrow Gate Effects in Micron and Submicron Mosfets (Device Simulation, Modeling)
Two-Dimensional Analysis of Narrow Gate Effects in Micron and Submicron Mosfets (Device Simulation, Modeling)
Chung, Shao-Shiun

Thumbnail for Automatic Bias Generation for Biased Random Instruction Generation
Automatic Bias Generation for Biased Random Instruction Generation
Bose, Mrinal

Thumbnail for A Theory for Algorithm-Based Fault Tolerance in Array Processor Systems
A Theory for Algorithm-Based Fault Tolerance in Array Processor Systems
Banerjee, Prithviraj

Thumbnail for Experimental Fault Characterization of a Neural Network
Experimental Fault Characterization of a Neural Network
Tan, Chang-Huong

Thumbnail for Compiler-Assisted Multiple Instruction Retry
Compiler-Assisted Multiple Instruction Retry
Li, Chung-Chi Jim; Chen, Shyh-Kwei; Fuchs, W. Kent; Hwu, Wen-Mei W.

Thumbnail for Reliable spin-based computing systems
Reliable spin-based computing systems
Patil, Ameya D

Thumbnail for Incremental algorithms for General Purpose Layout System
Incremental algorithms for General Purpose Layout System
Cynn, Myong Heon

Thumbnail for The Communication Complexity of Distributed Computing and a Parallel Algorithm for Polynomial Roots
The Communication Complexity of Distributed Computing and a Parallel Algorithm for Polynomial Roots
Tiwari, Prasoon

Thumbnail for Characterization, Design, and Modeling of on -Chip Electrostatic Discharge Protection Devices
Characterization, Design, and Modeling of on -Chip Electrostatic Discharge Protection Devices
Li, Junjun

Thumbnail for Reliability and Security Engine: A Processor-Level Framework for Application -Aware Detection and Recovery
Reliability and Security Engine: A Processor-Level Framework for Application -Aware Detection and Recovery
Nakka, Nithin Manikyam

Thumbnail for Spectroscopic characterization of the near-surface electronic structure of surface-modified III-V semiconductors
Spectroscopic characterization of the near-surface electronic structure of surface-modified III-V semiconductors
Dorsten, Jeffrey F.

Thumbnail for Placement by Simulated Evolution
Placement by Simulated Evolution
Kling, Ralph Michael

Thumbnail for Timing and Area Optimization for Standard-Cell VLSI Circuit Design
Timing and Area Optimization for Standard-Cell VLSI Circuit Design
Chuang, Weitong; Sapatnekar, Sachin S.; Hajj, Ibrahim N.

Thumbnail for Efficient Testing for Bridging Faults in Digital Integrated Circuits
Efficient Testing for Bridging Faults in Digital Integrated Circuits
Chen, Tzu-Hao

Thumbnail for New PCM based FPGA architecture and graphene memory cell design
New PCM based FPGA architecture and graphene memory cell design
Wei, Chunan

Thumbnail for Soft N-modular redundancy: exploiting statistics for robust computation
Soft N-modular redundancy: exploiting statistics for robust computation
Kim, Eric P.