University of Illinois Urbana-Champaign

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Showing 181–210 of 643 items
Thumbnail for Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Parallel Processing Techniques for the Simulation of MOS VLSI Circuits Using Waveform Relaxation
Smart, David William

Thumbnail for Novel many-core architectures for energy-efficiency
Novel many-core architectures for energy-efficiency
Karpuzcu, Rahmet

Thumbnail for Parallel architectural simulations on shared memory multiprocessors
Parallel architectural simulations on shared memory multiprocessors
Konas, Pavlos

Thumbnail for Design and implementation of low cost multi-gigabit OEIC receivers for the serial and parallel optical data links
Design and implementation of low cost multi-gigabit OEIC receivers for the serial and parallel optical data links
Shih, Chian-Gauh

Thumbnail for Design of Energy Efficient SOC With PIM Architecture and Deep Submicron Circuit Techniques
Design of Energy Efficient SOC With PIM Architecture and Deep Submicron Circuit Techniques
Yoo, Seung-Moon

Thumbnail for Optical and Electronic Properties, Nanoscale Structural Order, and Transformation Kinetics of Phase Change Materials
Optical and Electronic Properties, Nanoscale Structural Order, and Transformation Kinetics of Phase Change Materials
Lee, Bong-Sub

Thumbnail for High-Speed Silicon-Germanium BiCMOS and Indium Phosphide DHBT Receiver ICs for Optical and Wireless Communications
High-Speed Silicon-Germanium BiCMOS and Indium Phosphide DHBT Receiver ICs for Optical and Wireless Communications
He, Qiurong

Thumbnail for Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip
Low-Power CMOS Circuits for High-Performance Deep Submicron System on a Chip
Kim, Chulwoo

Thumbnail for Timing Analysis and Behavioral Synthesis with Process Variation
Timing Analysis and Behavioral Synthesis with Process Variation
Lucas, Gregory M.

Thumbnail for Diagnostic test set evaluation and enhancement
Diagnostic test set evaluation and enhancement
Hartanto, Ismed D.S.

Thumbnail for Modeling and Characterization of Heterojunction Bipolar Transistors
Modeling and Characterization of Heterojunction Bipolar Transistors
Mazhari, Baquer

Thumbnail for Common-case optimized memory hierarchy for data centers and HPC systems
Common-case optimized memory hierarchy for data centers and HPC systems
Jian, Xun

Thumbnail for Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Piecewise Linear Approach for Timing Simulation of VLSI Circuits on Serial and Parallel Computers
Tejayadi, Ongky

Thumbnail for Design guidelines and synthesis of a low dielectric constant inorganic composite for high performance microelectronic packaging
Design guidelines and synthesis of a low dielectric constant inorganic composite for high performance microelectronic packaging
Liu, Jay Guoxu

Thumbnail for PARASPICE: A parallel direct circuit simulator for shared-memory multiprocessors
PARASPICE: A parallel direct circuit simulator for shared-memory multiprocessors
Yang, Gung-Chung

Thumbnail for Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Design of a Bit-Sliced Processor Array with Built-In-Self-Test
Mui, Paul Chunhei

Thumbnail for Fault-Tolerant Algorithms for Multiple Processor Systems
Fault-Tolerant Algorithms for Multiple Processor Systems
Huang, Kuang-Hua

Thumbnail for Aggressive Code Improving Techniques Based on Control Flow Analysis
Aggressive Code Improving Techniques Based on Control Flow Analysis
Chang, Po-hua

Thumbnail for Back in the chips
Back in the chips
Bridges, Kenneth

Thumbnail for Reduction in Main Memory Traffic Through the Efficient Use of Local Memory
Reduction in Main Memory Traffic Through the Efficient Use of Local Memory
McNiven, Geoffrey David

Thumbnail for Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Enhancement of the Illinois Scan Architecture for Multiple Scan Inputs and Transition Faults
Shah, Mihir Atul

Thumbnail for Parallel algorithms for logic synthesis
Parallel algorithms for logic synthesis
De, Kaushik

Thumbnail for Register Transfer Level Design-for-Testability Methodology for a Frozen Clock Testing Strategy
Register Transfer Level Design-for-Testability Methodology for a Frozen Clock Testing Strategy
Slutter, Andrew Bryan

Thumbnail for The Summary of Engineering Research 2002
The Summary of Engineering Research 2002
University of Illinois at Urbana-Champaign. College of Engineering

Thumbnail for Efficient Array Addressing Techniques for Object-Based Systems
Efficient Array Addressing Techniques for Object-Based Systems
McNiven, Geoffrey David

Thumbnail for Testing infrastructure and other considerations in a waferscale processor
Testing infrastructure and other considerations in a waferscale processor
Liu, Jingyang

Thumbnail for Automated design of knowledge-lean heuristics: Learning, resource scheduling, and generalization
Automated design of knowledge-lean heuristics: Learning, resource scheduling, and generalization
Ieumwananonthachai, Arthur

Thumbnail for The Design of Programmable Logic Arrays With Concurrent Error Detection
The Design of Programmable Logic Arrays With Concurrent Error Detection
Mak, Gong-Po Philip

Thumbnail for Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
Compiler-Assisted Multiple Instruction Rollback Recovery Using a Read Buffer
Alewine, N.J.

Thumbnail for Lower and Upper-Bounds for the General Junction Routing Problem
Lower and Upper-Bounds for the General Junction Routing Problem
Maddila, Sanjeev Rao; Zhou, Dian