University of Illinois Urbana-Champaign

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Showing 1–19 of 19 items
Thumbnail for Profile-Guided Automatic Inline Expansion for C Programs
Profile-Guided Automatic Inline Expansion for C Programs
Chang, Pohua P.; Hwu, Wen-Mei W.

Thumbnail for Efficient Instruction Sequencing with Inline Target Insertion
Efficient Instruction Sequencing with Inline Target Insertion
Hwu, Wen-Mei W.; Chang, Pohua P.

Thumbnail for Using Profile Information to Assist Classic Code Optimizations
Using Profile Information to Assist Classic Code Optimizations
Chang, Pohua P.; Mahlke, Scott A.; Hwu, Wen-Mei W.

Thumbnail for The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
The Importance of Prepass Code Scheduling for Superscalar and Superpipelined Processors
Chang, Pohua P.; Lavery, Daniel M.; Hwu, Wen-Mei W.

Thumbnail for The Effect of Code Expanding Optimizations on Instruction Cache Design
The Effect of Code Expanding Optimizations on Instruction Cache Design
Chen, William Y.; Chang, Pohua P.; Conte, Thomas M.; Hwu, Wen-Mei W.

Thumbnail for IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors
IMPACT: An Architectural Framework for Multiple-Instruction-Issue Processors
Chang, Pohua P.; Mahlke, Scott A.; Chen, William Y.; Warter, Nancy J.; Hwu, Wen-Mei W.

Thumbnail for Three Superblock Scheduling Models for Superscalar and Superpipelined Processors
Three Superblock Scheduling Models for Superscalar and Superpipelined Processors
Chang, Pohua P.; Warter, Nancy J.; Mahlke, Scott A.; Chen, William Y.; Hwu, Wen-Mei W.

Thumbnail for Aggressive Code Improving Techniques Based on Control Flow Analysis
Aggressive Code Improving Techniques Based on Control Flow Analysis
Chang, Po-hua

Thumbnail for Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors
Architectural and Compiler Techniques for Energy Reduction in High-Performance Microprocessors
Bellas, Nikolaos

Thumbnail for rePLay: A Hardware Framework for Dynamic Program Optimization
rePLay: A Hardware Framework for Dynamic Program Optimization
Patel, Sanjay J.; Lumetta, Steven S.

Thumbnail for A high-level approach to test generation for VLSI circuits
A high-level approach to test generation for VLSI circuits
Narain, Prakash

Thumbnail for Compiler-Assisted Signature Monitoring
Compiler-Assisted Signature Monitoring
Warter, Nancy J.; Hwu, Wen-Mei W.

Thumbnail for Performance Aspects of Computers With Graphical User Interfaces
Performance Aspects of Computers With Graphical User Interfaces
Gupta, Aloke

Thumbnail for Modulo Scheduling for Control-Intensive General-Purpose Programs
Modulo Scheduling for Control-Intensive General-Purpose Programs
Lavery, Daniel Michael

Thumbnail for Systematic Computer Architecture Prototyping
Systematic Computer Architecture Prototyping
Conte, Thomas M.

Thumbnail for Modulo Scheduling with isomorphic control transformations
Modulo Scheduling with isomorphic control transformations
Warter, Nancy Jeanne

Thumbnail for Managing historic mountain landscapes near a modern city: the case of the Beijing Western Hills, 1912-2012
Managing historic mountain landscapes near a modern city: the case of the Beijing Western Hills, 1912-2012
Li, Zheng

Thumbnail for Annotating Mobile Code for Performance
Annotating Mobile Code for Performance
Jones, Joel

Thumbnail for Enhancing instruction-level parallelism through compiler-controlled speculation
Enhancing instruction-level parallelism through compiler-controlled speculation
Bringmann, Roger Alexander