University of Illinois Urbana-Champaign

Submit an Item
Browse
About

Title

Author(s)

Contributor(s)

Issue Date

From:

To:

Keyword(s)

Abstract

Series/Report Name or Number

Type of Resource

Permalink

Full Text

Academic Unit

College of Engineering 135
Dept. of Computer Science 117
Graduate Dissertations and Theses at Illinois 97
Dept. of Electrical and Computer Engineering 9
Research publications from UIUC 7
Summary of Engineering Research (1957-2008) 7
College of Liberal Arts and Sciences 6
School of Molecular and Cellular Biology 3
Universal Parallel Computing Research Center 3
Dept. of Biochemistry 2

Collection

Graduate Dissertations and Theses at Illinois 97
Dissertations and Theses - Computer Science 79
Research and Tech Reports - Computer Science 38
Dissertations and Theses - Electrical and Computer Engineering 7
Research publications from the University of Illinois at Urbana-Champaign 7
Summary of Engineering Research (2003-2008) 6
Research and Technical Reports - Universal Parallel Computing Research Center 3
Dissertations and Theses - Biochemistry 2
Senior Theses - Electrical and Computer Engineering 2
Bulletin - Illinois State Geological Survey 1

Author(s)

Adve, Sarita V. 8
University of Illinois at Urbana-Champaign. College of Engineering 6
Bocchino, Robert L., Jr. 4
Li, Man-Lap 4
Adve, Vikram S. 3
Baugh, Lee W. 3
Komuravelli, Rakesh 3
Lee, Adam J. 3
Li, Xiaodong 3
Lu, Shan 3

Keyword(s)

Computer Science 38
computer science 12
Computer Architecture 6
Research and publications sponsored in the College of Engineering 6
Approximate Computing 4
parallel systems 4
Compiler 3
Compilers 3
Approximation Tuning 2
Biology, Cell 2

Type of Resource

text 115
Thesis 15
image 1

↑ ↓

Showing 61–90 of 155 items

1
2
3 (current)
4
5

Thumbnail for Thread Escape Analysis for a Memory Consistency -Aware Compiler

Thread Escape Analysis for a Memory Consistency -Aware Compiler

Wong, Chi-Leung

Thumbnail for Thread Escape Analysis for a Memory Consistency-Aware Compiler

Thread Escape Analysis for a Memory Consistency-Aware Compiler

Wong, Chi-Leung

Thumbnail for Using Data Mining Techniques to Improve Software Reliability

Using Data Mining Techniques to Improve Software Reliability

Li, Zhenmin

Thumbnail for Soft Error Modeling and Analysis for Microprocessors

Soft Error Modeling and Analysis for Microprocessors

Li, Xiaodong

Thumbnail for Using Data Mining Techniques to Improve Software Reliability

Using Data Mining Techniques to Improve Software Reliability

Li, Zhenmin

Thumbnail for Thread Contracts for Race-Freedom

Thread Contracts for Race-Freedom

Karmani, Rajesh Kumar; Madhusudan, P.; Moore, Brandon

Thumbnail for Multicore construction of k-d trees with applications in graphics and vision

Multicore construction of k-d trees with applications in graphics and vision

Lu, Victor

Thumbnail for Practical analyses and transformations for flow-based parallelism

Practical analyses and transformations for flow-based parallelism

Chen, Nicholas Chun Y.

Thumbnail for Practical static race detection for Java parallel loops

Practical static race detection for Java parallel loops

Radoi, Cosmin

Thumbnail for Accelerating deep learning in the post-Moore’s era of computing

Accelerating deep learning in the post-Moore’s era of computing

Hegde, Kartik • 2023

Thumbnail for A New Framework for Hierarchical Cross-Layer Adaptation

A New Framework for Hierarchical Cross-Layer Adaptation

Sachs, Daniel Grobe

Thumbnail for Pose: Scalable General-Purpose Parallel Discrete Event Simulation

Pose: Scalable General-Purpose Parallel Discrete Event Simulation

Wilmarth, Terry L.

Thumbnail for CPU scheduling in robotics & AR/VR applications

CPU scheduling in robotics & AR/VR applications

Aditi, -

Thumbnail for Scalable and flexible bulk architecture

Scalable and flexible bulk architecture

Qian, Xuehai

Thumbnail for Transactional Programmability and Performance

Transactional Programmability and Performance

Baugh, Lee W.

Thumbnail for Transactional Programmability and Performance

Transactional Programmability and Performance

Baugh, Lee W.

Thumbnail for Cache Coherence in Embedded -Ring Multiprocessors

Cache Coherence in Embedded -Ring Multiprocessors

Strauss, Karin

Thumbnail for @tComment: testing Javadoc comments to detect comment-code inconsistencies

@tComment: testing Javadoc comments to detect comment-code inconsistencies

Tan, Shin Hwei

Thumbnail for Techniques to Mitigate the Effects of Congenital Faults in Processors

Techniques to Mitigate the Effects of Congenital Faults in Processors

Sarangi, Smruti R.

Thumbnail for Performance Aware Energy Efficient Storage Systems

Performance Aware Energy Efficient Storage Systems

Zhu, Qingbo

Thumbnail for Transactional Programmability and Performance

Transactional Programmability and Performance

Baugh, Lee W.

Thumbnail for Theories on the Evolution of the Spanish Unstressed Personal Pronouns

Theories on the Evolution of the Spanish Unstressed Personal Pronouns

Anderson, Alice Long

Thumbnail for Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors

Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors

Tiwari, Abhishek

Thumbnail for Performance Aware Energy Efficient Storage Systems

Performance Aware Energy Efficient Storage Systems

Zhu, Qingbo

Thumbnail for Improving failure diagnosis via better design and analysis of log messages

Improving failure diagnosis via better design and analysis of log messages

Yuan, Ding

Thumbnail for Automatic Recovery For Request Oriented Systems

Automatic Recovery For Request Oriented Systems

Lenharth, Andrew D.

Thumbnail for Understanding, Detecting and Exposing Concurrency Bugs

Understanding, Detecting and Exposing Concurrency Bugs

Lu, Shan

Thumbnail for Bulk Operation and Data Coloring for Multiprocessor Programmability

Bulk Operation and Data Coloring for Multiprocessor Programmability

Ceze, Luis H.

Thumbnail for Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors

Architectural Techniques to Mitigate the Effect of Spatial and Temporal Variations in Processors

Tiwari, Abhishek

Thumbnail for Speculative Shared -Memory Architectures

Speculative Shared -Memory Architectures

Martinez, Jose Fernando

1
2
3 (current)
4
5

Contact us for questions and to provide feedback.

Your Name (optional)

Your Email (optional)

Your Comment

What is 3 + 0?

© 2023 University of Illinois Board of Trustees

Log In

I don't have an Illinois NetID

Use this login method if you don't have an @illinois.edu email address. (Oops, I do have one)

IDEALS migrated to a new platform on June 23, 2022. If you created your account prior to this date, you will have to reset your password using the forgot-password link below.

Email

Password

(I forgot my password)