VEBoC: Variation and Error-Aware Design for Billions of Devices on a Chip
Author(s)
Akram, Shoaib
Cromar, Scott A.
Lucas, Gregory
Papakonstantinou, Alexandros
Chen, Deming
Issue Date
2008-04-08
Keyword(s)
integrated circuit design
system-on-chip
application-specific multicore
deep submicron technology
error-resilient computation
holistic error modeling
onchip parameter variations
soft-hard errors
variation-aware synthesis
Date of Ingest
2009-03-03T21:41:13Z
Abstract
Billions of devices on a chip is around the corner and the trend of deep submicron (DSM) technology scaling will continue for at least another decade. Meanwhile, designers also face severe on-chip parameter variations, soft/hard errors, and high leakage power. How to use these billions of devices to deliver power-efficient, high-performance, and yet error-resilient computation is a challenging task. In this paper, we attempt to demonstrate some of our perspectives to address these critical issues. We elaborate on variation-aware synthesis, holistic error modeling, reliable multicore, and synthesis for application-specific multicore. We also present some of our insights for future reliable computing.
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