University of Illinois Urbana-Champaign

Phase-locked loop using time-based integral control

Zhu, Junheng

Content Files
ZHU-THESIS-2016.pdf

Permalink

https://hdl.handle.net/2142/93044

Description

Title
Phase-locked loop using time-based integral control
Author(s)
Zhu, Junheng
Issue Date
2016-07-08
Director of Research (if dissertation) or Advisor (if thesis)
Hanumolu, Pavan Kumar
Department of Study
Electrical & Computer Eng
Discipline
Electrical & Computer Engr
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
M.S.
Degree Level
Thesis
Date of Ingest
2016-11-10T18:42:51Z
Keyword(s)
  • Phase-locked loop
  • Oscillators as Integrators
  • Ring oscillator
  • Current-controlled ring oscillator
  • Pulse-width-modulated control
  • Spur
  • Jitter
Abstract
This thesis explores the time-based techniques in the context of phase-locked loop (PLL) implementation. Many studies of the topic have been performed in the past. Functioning as an effective replacement of passive capacitors, time-based integrators using oscillators prove to be more area efficient and highly digital when implemented in integrated circuits. To better explore their potential area saving benefits, the time-based techniques are implemented to serve the integral control of a type-II PLL. A comprehensive analysis is performed to evaluate the pros and cons of the new techniques. In particular, the noise and power trade-off of having additional oscillators in the system is explained in detail. The analyses are veri ed with a prototype PLL fabricated in 65 nm CMOS technology. The prototype PLL occupies an active area of only 0.0021mm^2 and operates across a supply voltage range of 0.6V to 1.2V providing 0.4-to-2.6 GHz output frequencies. At 2.2 GHz output frequency, the PLL consumes 1.82mW at 1V supply voltage, and achieves 3.73 ps_rms integrated jitter. This translates to an FoM_J of -226.0 dB, which compares favorably with state-of-the-art designs while occupying the smallest reported active area. With the application of time-based techniques in clocking circuitry, the proposed time-based integral control PLL shall present a viable alternative to the conventional purely analog or digital PLL architectures.
Graduation Semester
2016-08
Type of Resource
text
Permalink
http://hdl.handle.net/2142/93044
Copyright and License Information
Copyright 2016 Junheng Zhu

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