K-hot pipelining

Lu, Dao

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https://hdl.handle.net/2142/93032 Copy

Description

Title

K-hot pipelining

Author(s)

Lu, Dao

Issue Date

2016-07-06

Director of Research (if dissertation) or Advisor (if thesis)

Kumar, Rakesh

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• Low-Energy and Low-Power Technologies
• Microarchitecture

Abstract

Computing systems in almost every application domain now support techniques to trade off power and performance. Such techniques are used to enforce power and thermal constraints, manage power and thermal budgets and respond to temperature and aging. Unfortunately, many of the current techniques are limited in the dynamic range they provide and scale poorly with technology. Techniques that can supplement or replace current techniques are needed. We propose k-hot pipelining, a novel technique to support multiple power-performance points in a processor. The key idea is to provide power and clock to only k stages of an m-stage pipeline (k < m); the k stages to be powered on change as instructions flow through the pipeline. Since the remaining m − k stages do not consume power, the technique results in power savings at the expense of performance. k-hot pipelining can be software or hardware-controlled, workload-agnostic or workload-adaptive, and can be used to provide power-performance points not supported by existing techniques. For one implementation of k-hot pipelining, we show that up to 49.9% power reduction is possible over the baseline design. Power reduction is up to 47% over the lowest power point supported by DVFS.

Graduation Semester

2016-08

Type of Resource

text

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http://hdl.handle.net/2142/93032

Copyright and License Information

Copyright 2016 Dao Lu

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