University of Illinois Urbana-Champaign

Process flow for built-in alignment mark in cleanroom

Zhou, Yunwen

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https://hdl.handle.net/2142/91578

Description

Title
Process flow for built-in alignment mark in cleanroom
Author(s)
Zhou, Yunwen
Contributor(s)
Zhu, Wenjuan
Issue Date
2016-05
Keyword(s)
  • nanotechnology
  • lithography
  • etching
  • deposition
  • metrology
  • silicon
Abstract
The purpose of fabricating the physical vapor deposition silicon (PVD-Si) wafer is to insert built-in alignment marks on it. To start with, there is a silicon wafer covered by a 100 nm-thick silicon dioxide layer, and then the entire process involves creating alignment marks/patterns on the wafer by photoresist and optics, to etch the substrate according to the patterns on the top layer, and to add a new oxidative layer on the substrate. It is necessary to use high-precision experimental equipment, for example, optical microscopy helps to verify the development condition during lithography step, and scanning electron microscope (SEM, the imaging technique for nanometer-scale resolution) helps to examine the top surface and/or the cross section during etching step. Furthermore, for achieving clear alignment marks, it is necessary to use chemicals which are caustic and/or toxic to remove water-immiscible residues, and it is helpful to use Freon reactive ion etcher (Freon RIE) instead of STS Advanced Silicon Etcher (STS ICP RIE) during silicon etching step. This thesis explains the theoretical principle of the entire process, introduces the tools and solutions used, and compares different recipes and their related results.
Type of Resource
text
Language
en
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http://hdl.handle.net/2142/91578

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