University of Illinois Urbana-Champaign

Design and analysis of ultra low power phase locked loop

Park, Seong Ho

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https://hdl.handle.net/2142/91558

Description

Title
Design and analysis of ultra low power phase locked loop
Author(s)
Park, Seong Ho
Contributor(s)
Hanumolu, Pavan Kumar
Issue Date
2016-05
Keyword(s)
  • internet of things
  • ultra low power
  • phase locked loop
Abstract
With the rising demand of Internet of Things devices, ultra low power systems recently have been a popular research topic; however, such systems have characteristically large power consumption. In response to this issue, an ultra low power phase locked loop is studied. This work includes analysis of a conventional phase locked loop, derivation of component parameters, proposal of an ultra low power phase locked loop architecture that consumes 92.75 nW at 15.4 MHz of oscillation with 500 mV supply voltage.
Type of Resource
text
Language
en
Permalink
http://hdl.handle.net/2142/91558

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