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https://hdl.handle.net/2142/91546
Description
Title
Design of a low-power PLL
Author(s)
Ko, Hyun Jae
Contributor(s)
Hanumolu, Pavan Kumar
Issue Date
2016-05
Keyword(s)
phase-locked loop
low power
Abstract
Nowadays, the main trend of designing a chip is to make it consume low power and occupy as small area as possible. Phase-locked Loop(PLL) is widely used in analog, digital, RF and communication systems. PLL is mostly used as a clock generator which produces a clock signal that synchronizes a circuit’s operation. CMOS technology is commonly used in making integrated circuits. This thesis focuses on the simulation and design of low power CMOS PLL integrated circuits using 180 μm technology. The first section of the thesis will present the most conventional analog PLL. Then in the second section a proposed design of PLL will be discussed.
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