VAST-LP: clock gating in high-level synthesis

Sun, Zelei

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https://hdl.handle.net/2142/90970 Copy

Description

Title

VAST-LP: clock gating in high-level synthesis

Author(s)

Sun, Zelei

Issue Date

2016-04-28

Director of Research (if dissertation) or Advisor (if thesis)

Chen, Deming

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Keyword(s)

• low power
• high level synthesis

Abstract

High-level synthesis (HLS) promises high-quality hardware with minimal develop- ment e ort. In this thesis, we evaluate the current state-of-the-art HLS engine VAST and propose a method to generate clock-gating-friendly RTL code for downstream logic synthesis tools. We use one-hot-key encoding method to build the state tran- sition in hardware, and we use the state registers along with main clock signal to generate subclock signals. By analyzing the usage of each register when the nite state machine is in di erent states, we assign the corresponding subclock signals to the register and reduce the unnecessary toggle of the registers when they are not in use. CHStone benchmarks in di erent application categories are used to verify the functionality and test the performance of the designs. The area and power data are measured using downstream commercial state-of-the-art tools during logic synthesis. We gain 5% to 20% dynamic power saving with -6% to 2% area increase.

Graduation Semester

2016-05

Type of Resource

text

Permalink

http://hdl.handle.net/2142/90970

Copyright and License Information

Copyright 2016 Zelei Sun

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