Design of energy efficient high speed I/O interfaces

Talegaonkar, Mrunmay Vyankatesh

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https://hdl.handle.net/2142/90871 Copy

Description

Title

Design of energy efficient high speed I/O interfaces

Author(s)

Talegaonkar, Mrunmay Vyankatesh

Issue Date

2016-03-15

Director of Research (if dissertation) or Advisor (if thesis)

Hanumolu, Pavan Kumar

Doctoral Committee Chair(s)

Hanumolu, Pavan Kumar

Committee Member(s)

• Kumar, Rakesh
• Rosenbaum, Elyse
• Shanbhag, Naresh

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

Ph.D.

Degree Level

Dissertation

Keyword(s)

• digital multiplying delay-locked loop (MDLL)
• digitally-controlled ring oscillator (DCO)
• bit error rate
• rapid on-off bias
• fast turn-on clock multiplier
• energy-proportional operation
• current mode logic output driver
• clock and data recovery (CDR), Mueller-Muller CDR
• baud-rate
• burst-mode
• channel pulse response
• channel estimation
• phase-locked loop (PLL)
• fractional-N PLL
• frequency-to-digital converter
• phase interpolator

Abstract

Energy efficiency has become a key performance metric for wireline high speed I/O interfaces. Consequently, design of low power I/O interfaces has garnered large interest that has mostly been focused on active power reduction techniques at peak data rate. In practice, most systems exhibit a wide range of data transfer patterns. As a result, low energy per bit operation at peak data rate does not necessarily translate to overall low energy operation. Therefore, I/O interfaces that can scale their power consumption with data rate requirement are desirable. Rapid on-off I/O interfaces have a potential to scale power with data rate requirements without severely affecting either latency or the throughput of the I/O interface. In this work, we explore circuit techniques for designing rapid on-off high speed wireline I/O interfaces and digital fractional-N PLLs. A burst-mode transmitter suitable for rapid on-off I/O interfaces is presented that achieves 6 ns turn-on time by utilizing a fast frequency settling ring oscillator in digital multiplying delay-locked loop and a rapid on-off biasing scheme for current mode output driver. Fabricated in 90 nm CMOS process, the prototype achieves 2.29 mW/Gb/s energy efficiency at peak data rate of 8 Gb/s. A 125X (8 Gb/s to 64 Mb/s) change in effective data rate results in 67X (18.29 mW to 0.27 mW) change in transmitter power consumption corresponding to only 2X (2.29 mW/Gb/s to 4.24 mW/Gb/s) degradation in energy efficiency for 32-byte long data bursts. We also present an analytical bit error rate (BER) computation technique for this transmitter under rapid on-off operation, which uses MDLL settling measurement data in conjunction with always-on transmitter measurements. This technique indicates that the BER bathtub width for 10^(−12) BER is 0.65 UI and 0.72 UI during rapid on-off operation and always-on operation, respectively. Next, a pulse response estimation-based technique is proposed enabling burst-mode operation for baud-rate sampling receivers that operate over high loss channels. Such receivers typically employ discrete time equalization to combat inter-symbol interference. Implementation details are provided for a receiver chip, fabricated in 65nm CMOS technology, that demonstrates efficacy of the proposed technique. A low complexity pulse response estimation technique is also presented for low power receivers that do not employ discrete time equalizers. We also present techniques for implementation of highly digital fractional-N PLL employing a phase interpolator based fractional divider to improve the quantization noise shaping properties of a 1-bit ∆Σ frequency-to-digital converter. Fabricated in 65nm CMOS process, the prototype calibration-free fractional-N Type-II PLL employs the proposed frequency-to-digital converter in place of a high resolution time-to-digital converter and achieves 848 fs rms integrated jitter (1 kHz-30 MHz) and -101 dBc/Hz in-band phase noise while generating 5.054 GHz output from 31.25 MHz input.

Graduation Semester

2016-05

Type of Resource

text

Permalink

http://hdl.handle.net/2142/90871

Copyright and License Information

Copyright 2016 Mrunmay Vyankatesh Talegaonkar

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