Time-based low dropout regulator

Wang, Danyang

Permalink

https://hdl.handle.net/2142/90671 Copy

Description

Title

Time-based low dropout regulator

Author(s)

Wang, Danyang

Issue Date

2016-04-27

Director of Research (if dissertation) or Advisor (if thesis)

Hanumolu, Pavan K.

Department of Study

Electrical & Computer Eng

Discipline

Electrical & Computer Engr

Degree Granting Institution

University of Illinois at Urbana-Champaign

Degree Name

M.S.

Degree Level

Thesis

Date of Ingest

2016-07-07T19:58:14Z

Keyword(s)

• Low dropout regulator
• Analog

Abstract

The low dropout regulator (LDO) is an essential building block for modern integrated circuits. Traditional analog design faces formidable challenges as technology scales down, such as lower supply voltage and channel length modulation. Digital LDOs do not have the problems that analog LDOs have, but they usually have worse performance metrics. Therefore, a time-based LDO is proposed to combine the merits of both analog and digital together. In the end, the LDO achieves 0.6-1 V supply voltage range and 0.5-0.9 V output voltage range. The maximum output current is 50 mA and the worst case transient time is 1.58 μs under 0.6 V supply voltage. The maximum current efficiency is 99.98%.

Graduation Semester

2016-05

Type of Resource

text

Permalink

http://hdl.handle.net/2142/90671

Copyright and License Information

Copyright 2016 Danyang Wang

Owning Collections