Layout Extraction Including Substrate Parasitics for ESD Protection Circuits and Design Rule Checking
Li, Qiao
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https://hdl.handle.net/2142/81993
Description
Title
Layout Extraction Including Substrate Parasitics for ESD Protection Circuits and Design Rule Checking
Author(s)
Li, Qiao
Issue Date
2001
Doctoral Committee Chair(s)
Sun-Mo (Steve) Kang
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
ESD design rule checking is different from the conventional design rule checking in that not only different rules have to be applied for different components in the ESD protection circuit, but also style of layout is of utmost importance to ensure uniform current distribution during ESD events. ESDRC first employs iLEX to extract the netlist from layout and identify the functionality of each layout object through LVS of the extracted netlist and the schematic. Specific ESD design rules are then checked for each layout object identified.
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