Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Hamzaoglu, Ilker
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Permalink
https://hdl.handle.net/2142/81957
Description
Title
Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
Author(s)
Hamzaoglu, Ilker
Issue Date
1999
Doctoral Committee Chair(s)
Patel, Janak H.
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Finally, we propose a new synthesis technique for reducing the test application time of counter-based exhaustive built-in-self-test test pattern generators. This technique reduces the test application time by reducing the size of the binary counter used in the counter-based test pattern generators.
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