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https://hdl.handle.net/2142/81934
Description
Title
The Retiming and Routing of VLSI Circuits
Author(s)
Saxena, Prashant
Issue Date
1998
Doctoral Committee Chair(s)
Liu, C.L.
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Mathematics
Language
eng
Abstract
"Multi-layer technologies present additional challenges to the routing of the nets because the layer assignment can have a large impact on the net delays. Traditional approaches cause the first few nets to monopolize the ""good"" layers. Therefore, they perform poorly under the metric of minimizing the maximum net delay. We propose the use of dynamic area quotas to remedy this problem. Our approach is independent of the routing model and the router used, and works very well in practice."
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