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https://hdl.handle.net/2142/81926
Description
Title
Logic Synthesis for Engineering Changes
Author(s)
Hsieh, Chang-Chao
Issue Date
1998
Doctoral Committee Chair(s)
Muroga, Saburo
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
In the optimization phase, the Transduction method and the delay-reducing/delay-restricted Transduction method are employed to minimize the area or delay of the already rectified network. Compatible sets of permissible functions are utilized to increase the effectiveness of optimization. The final network produced by SYLON-EC is both rectified and optimized.
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