Worst-Case Timing Analysis of Concurrently Executing DMA I/O and Programs
Huang, Tai-Yi
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https://hdl.handle.net/2142/81899
Description
Title
Worst-Case Timing Analysis of Concurrently Executing DMA I/O and Programs
Author(s)
Huang, Tai-Yi
Issue Date
1997
Doctoral Committee Chair(s)
Liu, Jane W.S.
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
A cycle-stealing DMA I/O task is allowed to proceed only when the CPU does not need the system bus. As a result, the execution time of a cycle-stealing DMA I/O task is affected by a set of CPU tasks which execute concurrently with the I/O task. We discuss the problem of bounding the WCET of a cycle-stealing DMA I/O task under a workload which consists of a set of independent CPU tasks. Each CPU task has an arbitrary release time. We use the dynamic programming technique to bound the WCET of the I/O task.
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