Tradeoffs in Designing Massively Parallel Accelerator Architectures
Mahesri, Aqeel A.
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Permalink
https://hdl.handle.net/2142/81853
Description
Title
Tradeoffs in Designing Massively Parallel Accelerator Architectures
Author(s)
Mahesri, Aqeel A.
Issue Date
2009
Doctoral Committee Chair(s)
Patel, Sanjay J.
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
We propose a methodology for performing an integrated optimization of both the micro-architecture and the physical circuit design of the cores and caches. In our approach, we use statistical sampling of the design space for evaluating the performance of the micro-architecture and RTL synthesis to characterize the area-power-delay of the underlying circuits. This integrated methodology enables a much more powerful analysis of the performance-area and performance-power tradeoffs for the low level micro-architecture. We use this methodology to find the optimal design points for an accelerator architecture under area constraints and power constraints. Our results indicate that more complex architectures scale well in terms of performance per area, but that the addition of a power constraint favors simpler architectures.
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