Techniques to Mitigate the Effects of Congenital Faults in Processors
Sarangi, Smruti R.
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Permalink
https://hdl.handle.net/2142/81768
Description
Title
Techniques to Mitigate the Effects of Congenital Faults in Processors
Author(s)
Sarangi, Smruti R.
Issue Date
2007
Doctoral Committee Chair(s)
Torrellas, Josep
Department of Study
Computer Science
Discipline
Computer Science
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
Using this model we introduce a novel framework that shows how microarchitecture techniques can mitigate variation-induced errors and even trade them off for power and processor frequency. Several such techniques are analyzed---in particular, a high-dimensional dynamic-adaptation technique that maximizes performance when there is slack in variation-induced error rate and power. The results show that our best combination of techniques increases processor frequency by 61% on average, allowing the processor to cycle 26% faster than without variation. Processor performance increases by 44% on average, resulting in a performance that is 18% higher than without variation---at only a 12.5% area cost.
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