Crosstalk Noise and Timing Analysis of Digital VLSI Circuits With Coupled Interconnects
Lu, Ninglong
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https://hdl.handle.net/2142/81355
Description
Title
Crosstalk Noise and Timing Analysis of Digital VLSI Circuits With Coupled Interconnects
Author(s)
Lu, Ninglong
Issue Date
2000
Doctoral Committee Chair(s)
Hajj, Ibrahim N.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
At the logic hierarchical level, we have developed a logic-level timing analyzer that will perform static timing simulation as well m coupling noise estimation using the information produced during the circuit hierarchy stage. The results of this analyzer consist of (a) critical path delay for the entire circuit, (b) transition windows, and (c) crosstalk noises for all victim gates. The maximum amplitude and effective width of crosstalk can be obtained at the fan-out of each victim gate and used to check the failure criteria of the gate that receives this noise pulse as an input.
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