Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits
Bobba, Sudhakar
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https://hdl.handle.net/2142/81345
Description
Title
Input-Pattern-Independent Estimation of Peak Current, Peak Power Dissipation, and Maximum Voltage Variation in the Power Distribution Network of VLSI Circuits
Author(s)
Bobba, Sudhakar
Issue Date
2000
Doctoral Committee Chair(s)
Hajj, Ibrahim N.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Technology scaling improves the performance of circuits, but also increases the interactions between elements and increases the internal stresses in the circuit. For the design of reliable circuits, estimation of the worst-case attributes of the electrical/thermal interactions and the internal stresses is required. In this dissertation, the problem of estimating the worst-case electrical/thermal interactions and the internal stresses is formulated as the maximization of weighted switching activity (or logic state) of a set of logic gates in subintervals of a clock cycle or in a clock cycle. Upper-bound estimates of the attributes of the electrical/thermal interactions and the internal stresses can then be computed by solving the optimization problem. This technique is applied to the computation of maximum switching activity, peak current for programmable logic arrays (PLAs), peak current envelope for static circuits, maximum leakage current, and the maximum voltage variation in the power distribution network. Comparisons with the results obtained by exhaustive simulation or simulation with a large number of random input vectors are also presented. In addition, design techniques for power-supply noise minimization, enhancing the circuit tolerance to power-supply voltage variations, and ultra-low power circuit design with significantly reduced current/power demand are presented.
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