A Fast Timing Simulator With Accurate Reduced-Order Interconnect Models
Kutuk, Haydar
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https://hdl.handle.net/2142/81322
Description
Title
A Fast Timing Simulator With Accurate Reduced-Order Interconnect Models
Author(s)
Kutuk, Haydar
Issue Date
2000
Doctoral Committee Chair(s)
Kang, Sung-Mo (Steve)
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
The methodologies and techniques developed in this research are implemented in a fast interconnect/timing simulator, ILLIADS-I. In their practical implementation the robustness of the interconnect models is further improved to achieve absolute numerical stability in addition to their theoretical passivity and stability. Unlike other approaches, the interconnect simulation methods in ILLIADS-I do not handle the interconnect network separately for obtaining and then placing a corresponding stamp into a SPICE-like simulator. The accuracy and speed have been demonstrated for a number of circuits for various loads and input waveforms. Experimental results show that ILLIADS-I is both accurate and fast. The speed advantage is shown to increase with the circuit size for multilevel interconnect networks with nonlinear driver and load circuits. In addition to ILLIADS-I, a stand-alone linear interconnect simulator called iPINTA (Illinois Passive Interconnect Analyzer) has been developed. This simulator is a complete tool for analyzing linear multiport interconnect networks based on interconnect simulation principles described in the thesis.
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