The Monolithic Integration of Enhancement- and Depletion-Mode High Electron Mobility Transistors for Low-Power and High-Speed Circuit Applications in the Lattice -Matched Indium Phosphide Material System
Mahajan, Aaditya
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https://hdl.handle.net/2142/81295
Description
Title
The Monolithic Integration of Enhancement- and Depletion-Mode High Electron Mobility Transistors for Low-Power and High-Speed Circuit Applications in the Lattice -Matched Indium Phosphide Material System
Author(s)
Mahajan, Aaditya
Issue Date
1999
Doctoral Committee Chair(s)
Adesida, Ilesanmi
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
By using a buried-Pt process in conjunction with proper heterostructure design, a procedure for the fabrication of enhancement-mode HEMTs (E-HEMTs) has been developed. Following the full characterization of E-HEMT devices, a heterostructure was then designed for the monolithic integration of E-HEMTs and D-HEMTs, using a two-level etch-stop process. Devices were successfully fabricated and characterized which showed the viability of a directcoupled FET logic (DCFL) circuit technology in the InP material system. To demonstrate the feasibility of this technology, DCFL ring oscillators were fabricated and tested. These circuits successfully demonstrated high-speed, low-power performance while utilizing only a single voltage supply.
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