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https://hdl.handle.net/2142/81250
Description
Title
High-Level Power Estimation
Author(s)
Nemani, Mahadevamurty
Issue Date
1998
Doctoral Committee Chair(s)
Farid N. Najm
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
High-level power estimation requires high-level predictions of circuit average activity, area, and delay, in order to estimate power. The main contribution of this research is development of predictors (estimators) for activity, area, and delay for combinational circuits, thus making it possible to estimate power at the RT level. All of the above predictors work with a functional description of the design and avoid the time consuming translation of the RT description into a circuit-level description, thus making them fast, which in turn enables the designer to explore the area, delay, and power space early in the design.
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