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https://hdl.handle.net/2142/81238
Description
Title
Interfacial Structures of Oxides on GaAs
Author(s)
Chou, Li-Jen
Issue Date
1998
Doctoral Committee Chair(s)
Hsieh, Kuang-Chien
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Materials Science
Language
eng
Abstract
For the deposited oxide/GaAs work, only deposition of (Ga,Gd)$\sb2$O$\sb3$ oxide among others shows a low interface trap density (D$\rm\sb{it})$ at the oxide-GaAs interface. It is low enough to warrant the demonstration of both n- and p-channel enhancement GaAs MOSFETs. High-resolution transmission electron microscopy (HRTEM) indicates that deposition of MgO, Al$\sb2$O$\sb3$, and Ga$\sb2$O$\sb3$, fail to yield a truly amorphous oxide. Although deposition of SiO$\sb2$ results in an amorphous oxide. There lacks a transition layer between SiO$\sb2$ and GaAs. A correlation between high-low frequency capacitance-voltage (C-V) phenomenon and physical interfacial structure property has been derived by HRTEM. A thin oxide epilayer on GaAs has been identified and proposed as the key factor to solve the surface dangling bond problem. X-ray photoelectron spectroscopy (XPS) and Auger data show that Gd rich in the interface region is the essential part of the good quality MOS devices. It suggest that carefully controlled the initial growth conditions such as substrate temperature, source temperature and oxide growth rate will directly affect the electrical property of the MOSFET.
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