Modeling, Simulation and Design of EOS/ESD Protection Devices and Circuits in Silicon-on-Insulator Technology
Raha, Prasun Kumar
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https://hdl.handle.net/2142/81229
Description
Title
Modeling, Simulation and Design of EOS/ESD Protection Devices and Circuits in Silicon-on-Insulator Technology
Author(s)
Raha, Prasun Kumar
Issue Date
1998
Doctoral Committee Chair(s)
Rosenbaum, Elyse
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
For the first time, a circuit level simulation tool for CMOS-on-SOI ESD protection networks is presented. The simulator, SOI-iETSIM, has built-in device models for completely coupled electrothermal simulation of SOI protection devices operating in the high current regime. The implementation of thermal models in a circuit level simulator for SOI circuits is discussed. Modeling the floating body effects in SOI MOSFETs and their effect on the device operation in the snapback mode is also discussed. The implementation of the parasitic BJT in the SOI MOSFET model is different from previously published models. Device simulation examples and an SOI-ESD protection circuit simulation example are also presented.
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