Hierarchical Simulation to Assess Hardware and Software Dependability
Ries, Gregory Lawrence
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https://hdl.handle.net/2142/81218
Description
Title
Hierarchical Simulation to Assess Hardware and Software Dependability
Author(s)
Ries, Gregory Lawrence
Issue Date
1997
Doctoral Committee Chair(s)
Iyer, Ravishankar K.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
The simulation method is demonstrated and validated in four case studies that analyze a commercial, high-speed networking system called Myrinet. One key result from the case studies shows that the simulation method predicts that same fault impact 87.5% of the time, as is obtained by similar fault injections into a real Myrinet system. Reasons for the remaining discrepancy are examined in the thesis. A second key result shows the reduction in the number of simulations needed due to the fault dictionary method. In one case study, 500 faults were injected at the chip level, but only 255 propagated to the system level. of these 255 faults, 110 shared identical fault dictionary entries at the system level and so did not need to be resimulated. The necessary number of system-level simulation was therefore reduced from 500 to 145. Finally, third result in the case studies shows how the simulation method can be used to improve the dependability of the target system. The simulation analysis was used to add recovery to the target software for the most common fault propagation mechanisms that would cause the software to hang. After the modification, the number of hangs was reduced by 60% for fault injection into the real system.
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