Design and Development of Cell Queuing, Processing, and Scheduling Modules for the iPOINT Input-Buffered ATM Testbed
Duan, Haoran
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https://hdl.handle.net/2142/81175
Description
Title
Design and Development of Cell Queuing, Processing, and Scheduling Modules for the iPOINT Input-Buffered ATM Testbed
Author(s)
Duan, Haoran
Issue Date
1997
Doctoral Committee Chair(s)
Sung-Mo Kang
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Physics, Optics
Language
eng
Abstract
During this research, a five-port IQ-based optoelectronic iPOINT ATM switch has been developed and demonstrated. It has been fully functional with an aggregate throughput of 800 Mb/s. The second-generation IQ-based switch is currently under development. Equipped with iiQueue modules and MUCS module, the new switch system will deliver a multi-gigabit aggregate throughput, eliminate HOL blocking, provide per-VC QoS, and achieve near-100% link bandwidth utilization. Complete documentation of input modules and trunk module for the existing testbed, and complete documentation of 3DQ, iiQueue, and MUCS for the second-generation testbed are given in this dissertation.
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