Architecture and CAD for Nanoscale and Three-Dimensional FPGA
Dong, Chen
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https://hdl.handle.net/2142/81158
Description
Title
Architecture and CAD for Nanoscale and Three-Dimensional FPGA
Author(s)
Dong, Chen
Issue Date
2010
Doctoral Committee Chair(s)
Chen, Deming
Department of Study
Electrical and Computer Engineering
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
To maximize the potential performance gain of 3D integrated circuit architectures, an SSTA engine was developed to deal with both uncorrelated and correlated variations in 3D FPGAs. The effects of intra-die and inter-die variation are considered. Using the 3D physical design tool TPR as a base, a new 3D routing algorithm is developed, which improves the average performance of two-layer designs by over 22% and three-layer designs by over 27%.
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