VLSI Physical Design for Manufacturability and Reliability
Deng, Liang
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https://hdl.handle.net/2142/81030
Description
Title
VLSI Physical Design for Manufacturability and Reliability
Author(s)
Deng, Liang
Issue Date
2007
Doctoral Committee Chair(s)
Wong, Martin D.F.
Department of Study
Electrical and Computer Engineering
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
In Chapter 2, we present an optimal algorithm to generate the twist pattern for the complementary bus structure, reducing the noise as well as handling design changes. In Chapter 3, another bus optimization is present to reduce the power consumption in memory address bus for specific applications. The energy dissipates to both coupling and self capacitances are considered during the optimization. A statistical shortest path algorithm is present in Chapter 4. Its applications, such as maze routing, timing analysis and buffer insertion, are discussed. Proposed algorithm can handle an arbitrary function of mean and variance of path weight instead of convex constraint needed for existing algorithms. In Chapter 5, buffer insertion under process variations is discussed in details. We proved that buffer insertion is not sensitive to process variations both theoretically and practically. In Chapter 6 and 7, design techniques are presented to improve the manufacturability. We present a novel metal fill insertion methodology in Chapter 6 for lithography. Trade-off between printability and coupling capacitance are considered. In Chapter 7, dummy features and boundary based method are proposed to enable the cell-wise optical proximity correction (OPC) for 32nm node and beyond. It will saves weeks of computation on full-chip OPC and reduce the exponentially increase mask data volume. Our proposed methodology will also lead to more accurate timing model for standard cell library with post-OPC information ready.
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