Reliability and Security Engine: A Processor-Level Framework for Application -Aware Detection and Recovery
Nakka, Nithin Manikyam
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https://hdl.handle.net/2142/80982
Description
Title
Reliability and Security Engine: A Processor-Level Framework for Application -Aware Detection and Recovery
Author(s)
Nakka, Nithin Manikyam
Issue Date
2006
Doctoral Committee Chair(s)
Ravishanker K. Iyer
Department of Study
Electrical and Computer Engineering
Discipline
Electrical and Computer Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
Our results show a decrease in overhead by 53% and a decrease in false positives by approximately 12% as compared to a duplication of all instructions. We detect all control logic errors that affect the instruction wakeup and scheduling mechanism. The combined hardware overhead due to the framework and modules is less than 10%. Our ongoing research is targeted towards implementing the framework and the modules on a Xilinx FPGA and towards refining the application analysis tools to detect key application characteristics, and then translating these characteristics into hardware modules that can be embedded into the framework.
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