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https://hdl.handle.net/2142/80964
Description
Title
Communication-Inspired Design of on -Chip Buses
Author(s)
Sridhara, Srinivasa Raghavan
Issue Date
2006
Doctoral Committee Chair(s)
Shanbhag, Naresh R.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Engineering, Electronics and Electrical
Language
eng
Abstract
We mitigate the effects of intersymbol interference by employing a variable threshold inverter as an equalizer and operate the bus at rates beyond the rate governed by RC delay of the interconnect. We demonstrate even higher speeds by combining equalization with crosstalk avoidance coding. Simulation results for a 10-mm 32-bit bus in 0.13-mum CMOS technology show that 1.28x speed-up is achievable by equalization alone and 2.30x speed-up is achievable by joint equalization and coding.
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