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https://hdl.handle.net/2142/80944
Description
Title
Dynamic Optimization in Hardware
Author(s)
Fahs, Brian Matthew
Issue Date
2005
Doctoral Committee Chair(s)
Patel, Sanjay J.
Lumetta, Steven S.
Department of Study
Electrical Engineering
Discipline
Electrical Engineering
Degree Granting Institution
University of Illinois at Urbana-Champaign
Degree Name
Ph.D.
Degree Level
Dissertation
Keyword(s)
Computer Science
Language
eng
Abstract
On a broad level, we describe the relationship between well-known compiler optimization concepts and hardware-implemented optimizations. We define and explore two hardware-centric dynamic optimization paradigms: continuous optimization and discrete optimization. Continuous optimization optimizes instructions in the processor pipeline prior to execution. It is primarily useful for reducing processor resource contention and increasing ILP. Discrete optimization captures reusable chunks of the dynamic instruction stream, optimizes them, and then sequences them back into execution. Its primary benefits come from reducing instruction count and increasing ILP. The benefits of these two models are mostly orthogonal, and, therefore, they can be combined to provide larger improvements than either approach could provide by itself.
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